Jordan Carlin
47452ddaaa
Remove hardcoded /opt/riscv
2024-07-23 23:29:45 -07:00
Rose Thompson
6c212ebf0e
Changes are confirmed to work on the FPGA.
2024-07-23 17:39:38 -05:00
Rose Thompson
35efbd6a54
Changes are confirmed to work on the FPGA.
2024-07-23 17:39:38 -05:00
Rose Thompson
7223b15134
Merge branch 'rvvi'
2024-07-22 12:01:01 -05:00
Rose Thompson
02f108345a
Merge branch 'rvvi'
2024-07-22 12:01:01 -05:00
David Harris
f30cc46ec5
Disable misaligned accesses in imperas configuration and check misaligned support requires D$
2024-07-21 08:26:07 -07:00
David Harris
f5f8a6c50c
Disable misaligned accesses in imperas configuration and check misaligned support requires D$
2024-07-21 08:26:07 -07:00
Rose Thompson
9471dcd296
Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.
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Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.
2024-07-19 17:08:47 -05:00
Jordan Carlin
5661dc4a03
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
2024-07-18 21:36:00 -07:00
Jordan Carlin
8853fd52bc
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
2024-07-18 21:36:00 -07:00
David Harris
29bd6a30ab
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-07-15 04:27:59 -07:00
David Harris
975c72c91d
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-07-15 04:27:59 -07:00
David Harris
459eaaef6a
Initial effort to make testbench_fp compatible with Verilator without breaking Questa
2024-07-14 20:08:33 -07:00
Rose Thompson
c53ea43ef9
Merge pull request #880 from davidharrishmc/dev
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wsim elf handling and RV64GCK lockstep support
2024-07-14 11:40:30 -05:00
Rose Thompson
276cb558f0
Merge pull request #880 from davidharrishmc/dev
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wsim elf handling and RV64GCK lockstep support
2024-07-14 11:40:30 -05:00
David Harris
26d4fbcc19
Switched ImperasDV to RV64GCK model to support crypto (issue #872 )
2024-07-13 21:42:14 -07:00
Rose Thompson
f83e6cf771
Fixed issue #874 .
2024-07-08 14:48:52 -05:00
Jordan Carlin
2528830e98
Merge remote-tracking branch 'upstream/main' into installation
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Fix derivgen.pl shebang conflict
2024-07-08 06:46:41 -07:00
Jordan Carlin
09a061b580
Merge remote-tracking branch 'upstream/main' into installation
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Fix derivgen.pl shebang conflict
2024-07-08 06:46:41 -07:00
David Harris
84c687080d
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-07-05 21:42:26 -07:00
David Harris
9f5e7b8653
Merge pull request #851 from kevindkim723/intdivb
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Reduce Bit widths for IDIV on FPU
2024-07-05 21:42:19 -07:00
David Harris
9279b2d56a
Added imperas configuration for Lee
2024-07-05 09:13:18 -07:00
David Harris
775930ae4f
Fixes to memfile generation for rv32. Updated new misa.B in imperas.ic, but need new version of ImperasDV to test
2024-07-04 07:36:56 -07:00
Jordan Carlin
838e44a53f
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
2024-07-03 23:44:25 -07:00
Jordan Carlin
0459c68615
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
2024-07-03 23:44:25 -07:00
Jordan Carlin
e6e070f4e4
Update python shebangs to use /usr/bin/env python3 so virtual environment can be used (also aids in general portability)
2024-07-03 20:42:55 -07:00
Jordan Carlin
7419689359
Update python shebangs to use /usr/bin/env python3 so virtual environment can be used (also aids in general portability)
2024-07-03 20:42:55 -07:00
David Harris
8645441d00
Testbench automatically creates memfile, label, addr files if they are out of date or missing
2024-07-03 16:52:16 -07:00
David Harris
a2fb6a21c5
Removed testbench-imperas now that wsim supports lockstep and single ELF files
2024-07-03 06:25:32 -07:00
David Harris
e72c8b8e09
Watchdog timeout on buildroot boot is a halting criteria
2024-07-02 14:22:51 -07:00
David Harris
38b0c10f9b
Updated wallyTracer to be compatible with VCS
2024-07-02 04:47:53 -07:00
Jordan Carlin
c33ad35b75
Remove verilator hack
2024-06-28 17:28:43 -07:00
Jordan Carlin
5634577a24
Remove verilator hack
2024-06-28 17:28:43 -07:00
David Harris
bf9fdcf9f9
Cleaned up lint errors in testbench_fp; still not working in Verilator because readvectors receives the wrong unit, fmt, opctrl
2024-06-27 04:26:56 -07:00
Jordan Carlin
784151e165
Fix testbench_fp to use F_SUPPORTED, not S_SUPPORTED
2024-06-26 22:29:00 -07:00
Jordan Carlin
221f710baf
Use QUESTA as flag for
2024-06-26 21:18:40 -07:00
Kevin Kim
4877633977
lint fixes tests vh
2024-06-21 22:16:09 -07:00
Kevin Kim
19f0cf7a35
putting back tests in tests vh
2024-06-21 21:51:44 -07:00
Kevin Kim
00bf3faa9c
changed intdivb width
2024-06-21 21:31:19 -07:00
Jordan Carlin
b76941d278
Use VCS built-in default macro instead of defining SIM_VCS
2024-06-21 15:17:59 -07:00
Ross Thompson
1c6ebb86a3
Added some debug code to count frames sent to the ethernet mac and frames sent to the phy.
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Removed the external reset of the phy and now it always reliably starts in the same way. The first 0x117 frames are always captured.
2024-06-20 12:54:12 -07:00
Rose Thompson
e1fc44a5bf
Merge pull request #849 from davidharrishmc/dev
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lint cleanup and divider optimization
2024-06-20 09:04:19 -07:00
David Harris
d8d94eeafa
Merge pull request #808 from jordancarlin/main
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Update riscv-arch-test
2024-06-20 08:43:41 -07:00
Jordan Carlin
90f5a4ef48
Only run fmsub_b15 for f_fma test
2024-06-20 07:48:33 -07:00
David Harris
25780f53ce
Fixed Verilator testbench issue from FunctionName by rolling back to old if. PC=0 detection is disabled for now.
2024-06-20 00:57:58 -07:00
Ross Thompson
d368f2e77e
Removed *** from testbench.
2024-06-19 13:51:37 -07:00
Ross Thompson
5e5ca0809f
Removed more *** from lsu and updated assertions for dtim.
2024-06-19 10:52:51 -07:00
Jordan Carlin
156bfc0387
Update f_fma tests to use smaller files from riscv-arch-test
2024-06-18 23:38:03 -07:00
Jordan Carlin
d58b454a8b
Finish switching Zfa to use riscv-arch-test
2024-06-18 23:31:37 -07:00
Jordan Carlin
955f5d831f
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-06-18 22:39:05 -07:00
David Harris
ecae1100f6
Lint cleanup
2024-06-18 05:49:49 -07:00
David Harris
4a4bbdfc43
More code cleanup
2024-06-14 09:50:07 -07:00
David Harris
53477b2c85
Code cleanup
2024-06-14 07:08:17 -07:00
David Harris
b1c9450b4a
Code cleanup: RAM, fdivsqrt
2024-06-14 03:35:05 -07:00
David Harris
312c9c9f55
Updated logger to new IClass signal name
2024-06-12 07:24:05 -07:00
Ross Thompson
563980443a
Merge branch 'main' into rvvi
2024-06-10 18:10:23 -07:00
Jordan Carlin
c560a0ae8f
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-06-01 23:22:30 -07:00
Rose Thompson
48fd365b9d
Still don't understand why wally.do can't load testbench.sv with functional coverage. But wally-imperas-cov.do can load testbench.sv with functional coverage.
2024-05-28 13:00:17 -05:00
Rose Thompson
92ee56c1a1
Yay. Finally found the bug which prevented wally.do from having functional coverage using riscvISACOV.
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testbench.sv was missing the trace2cov instance.
2024-05-27 17:25:20 -05:00
Jordan Carlin
6f79dca9c4
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-27 12:29:24 -07:00
Jordan Carlin
dcafe4793e
Add froundnx and fround.d tests
2024-05-24 15:16:35 -07:00
Rose Thompson
dc09e1c0c5
Modified names so they don't conflict with FPGA's axi signals.
2024-05-24 16:38:47 -05:00
Rose Thompson
73261e7f89
More cleanup. Close to the simpliest it can be.
2024-05-24 16:34:33 -05:00
Rose Thompson
bd2ec879d2
Removed unused axi signals from packetizer.
2024-05-24 16:31:27 -05:00
Rose Thompson
263be86119
Packetizer cleanup.
2024-05-24 16:27:09 -05:00
Rose Thompson
1f7d732dca
Moved the rvvisynth code to testbench since I only want this for simulation and fpga.
2024-05-24 16:10:58 -05:00
Jordan Carlin
f410bbb79e
Use Zfa tests from riscv-arch-test instead of wally-riscv-arch-test
2024-05-21 00:04:27 -07:00
Rose Thompson
6e3ccbb9c1
Almost have it working for both buildroot and single elfs.
2024-05-17 17:34:29 -05:00
Rose Thompson
224b2e4dc4
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-17 17:10:28 -05:00
Rose Thompson
0ed75a3ff5
Reverted testbench-imperas.sv incase someone wants this.
2024-05-17 16:48:29 -05:00
Rose Thompson
038aae388b
Yay. Finally found the issue with the integrated testbench.sv and imperasDV.
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The function which loads the elf file rvviRefInit must be called during an initial block
using a valid file name. Because of how the testbench was organized the elffile was not defined
until several cycles later so the call to rvviRefInit did not have a valid elf. Waiting several
cycles does not work. rvviRefInit requires being called in an initial block so it is not possible
to run back to back imperasDV simulations in the same run.
2024-05-17 16:45:01 -05:00
Rose Thompson
e6902eb4d2
Ok. How does it still work? testbench-imperas.sv the same as testbench.sv now.
2024-05-17 16:08:14 -05:00
Rose Thompson
d9807bb909
This is crazy. I'm merging testbench.sv into testbench-imperas.sv to find the point when it stops working. But each logical point where it would stop working it keeps working. For example moving readmemh from initial to always block.
2024-05-17 14:45:37 -05:00
Rose Thompson
a885240fbd
temporary commit to help debug merging testbench.sv with testbench-imperas.sv
2024-05-17 12:36:00 -05:00
Rose Thompson
62eaca0e6e
Almost working ImperasDV with testbench.sv and wally.do. For some reason IDV is saying the instructions are mismatching.
2024-05-16 17:01:25 -05:00
Rose Thompson
9a42aab971
Merge pull request #804 from jordancarlin/dev
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Eliminate more logical operators and replace with bitwise operators
2024-05-16 15:45:18 -05:00
Rose Thompson
8391b8b821
Progress towards unified regression.
2024-05-16 15:29:12 -05:00
Rose Thompson
08601d7270
Added functionallity to testbench.sv for single elf files.
2024-05-16 13:59:15 -05:00
Jordan Carlin
1d8ffee20c
Certain Zcb instructions are dependent on other extensions, not the entire extension
2024-05-15 19:16:43 -07:00
Jordan Carlin
ef778da98d
Eliminate more logical operators and replace with bitwise
2024-05-15 10:50:23 -07:00
Jordan Carlin
4ffce9a752
Switch riscvassertions to use bitwise operators instead of logical operators per Wally style guide
2024-05-15 09:23:24 -07:00
Rose Thompson
e295454948
Merge pull request #798 from jordancarlin/newConfig
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Update config to derive MISA from macros and update MISA bits based on the spec
2024-05-15 10:28:44 -05:00
Jordan Carlin
291d1e62d5
M implies Zmmul
2024-05-14 19:38:34 -07:00
Jordan Carlin
4a72922087
update config to derive MISA from macros
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- Remove C_SUPPORTED and update decompress unit based on Zc* extensions
- Derive A_SUPPORTED from A subextensions
- Derive B_SUPPORTED from B subextensions
- Derive C_SUPPORTED from C subextensions
2024-05-14 06:49:18 -07:00
David Harris
175c18da01
Parameterized FMA. However, some offsets are not parameterized. See PR #793 for list of changes
2024-05-13 15:16:00 -07:00
David Harris
d4ac53f000
commented legal TEST options
2024-05-13 07:22:30 -07:00
David Harris
75c10bddfa
Moved case.sh to tests/fp
2024-05-13 07:12:16 -07:00
David Harris
d0dad1d9f6
Fixed testbench_fp to use modified unpacker
2024-05-12 12:11:48 -07:00
David Harris
380d88fc68
Merged config-shared after fma fix
2024-05-12 11:10:55 -07:00
David Harris
009d251433
Fixed cvtint bug by adding 2 bits to convert width; initial implementation of fround passes basic regression but fails some nightly regression cases
2024-05-11 22:32:51 -07:00
David Harris
c0743a1fcf
Added missing convert F to/from Int64 tests for arch64f
2024-05-11 02:29:47 -07:00
Katherine Parry
807ef44772
fixed fma testfloat issue #578
2024-05-10 18:12:11 -07:00
Rose Thompson
ceb31fec68
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-10 08:54:23 -05:00
Rose Thompson
b027fa44ef
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-10 08:53:00 -05:00
Rose Thompson
4bd5d334df
Modified testbench so it instantiates the function logger if DEBUG is greater than 0 rather than just 1.
2024-05-10 08:51:59 -05:00
David Harris
66b33c09be
Added Zaamo and Zalrsc support to testbench and regression
2024-05-10 05:41:00 -07:00
David Harris
54750ae4d5
Fixed out-of-bound vector accesses in testbench_fp when FLEN < Q_LEN
2024-05-09 19:52:37 -07:00
David Harris
bdd0043cd1
Testbench terminates buildroot sim at instruction limit
2024-05-09 07:58:53 -07:00
David Harris
47af54b131
Fixed buildroot prematurely terminating in VCS
2024-05-09 07:29:45 -07:00
David Harris
0d1d59a3d8
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-05-08 18:58:01 -07:00
