Rose Thompson 9471dcd296 Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes. ... Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.		2024-07-19 17:08:47 -05:00
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common	Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.	2024-07-19 17:08:47 -05:00
coverage	pmp coverage	2024-05-02 11:53:32 -07:00
sdc	Remove all #delay from non-testbench.	2024-03-16 11:20:32 -07:00
testbench_fp.sv	Parameterized FMA. However, some offsets are not parameterized. See PR #793 for list of changes	2024-05-13 15:16:00 -07:00
testbench-imperas.sv	Still don't understand why wally.do can't load testbench.sv with functional coverage. But wally-imperas-cov.do can load testbench.sv with functional coverage.	2024-05-28 13:00:17 -05:00
testbench.sv	Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.	2024-07-19 17:08:47 -05:00
tests_fp.vh	testfloat running through wsim; moved lint, regression, wsim to bin directory so we don't need ./	2024-04-06 08:22:39 -07:00
tests.vh	Add froundnx and fround.d tests	2024-05-24 15:16:35 -07:00
wallywrapper.sv	Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.	2024-07-19 17:08:47 -05:00