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  • 19fc7d2381 refactored sim file bbracker 2021-03-05 14:25:16 -0500
  • 0f4a231543 first merge of ahb fix bbracker 2021-03-05 14:24:22 -0500
  • 1a11b60664 busybear: slight testbench update Noah Boorstin 2021-03-05 19:00:40 +0000
  • 2e2eb5839f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Thomas Fleming 2021-03-05 13:35:44 -0500
  • 8c97143be6 Place tlb parameters into constant header file Thomas Fleming 2021-03-05 13:35:24 -0500
  • 7e11317a2d Export SATP_REGW from csrs to MMU modules Thomas Fleming 2021-03-05 01:22:53 -0500
  • f48af209c4 busybear: make CSRs only weird for us Noah Boorstin 2021-03-05 00:46:32 +0000
  • 5a3ba1174e busybear: better implenetation of sim-busybear-batch Noah Boorstin 2021-03-05 00:39:03 +0000
  • a662aa487c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Ross Thompson 2021-03-04 17:31:27 -0600
  • 264480f258 updated the function radix to look at wally signals. Ross Thompson 2021-03-04 17:31:12 -0600
  • 41f682f848 Partial progress towards compressed instructions Jarred Allen 2021-03-04 18:30:26 -0500
  • dfae278ffb busybear: make imperas tests work again Noah Boorstin 2021-03-04 22:11:42 +0000
  • cfac6bf0c7 fixed various bugs Katherine Parry 2021-03-04 22:20:39 +0000
  • 09564f1c77 fixed various bugs Katherine Parry 2021-03-04 22:20:28 +0000
  • a6bc39b5ad fixed various bugs Katherine Parry 2021-03-04 22:20:23 +0000
  • 526e3f5996 fixed various bugs Katherine Parry 2021-03-04 22:20:02 +0000
  • 1e906b36a0 fixed various bugs Katherine Parry 2021-03-04 22:19:21 +0000
  • 3fb0f323b8 fixed various bugs Katherine Parry 2021-03-04 22:18:47 +0000
  • fdfc0dbf46 fixed various bugs Katherine Parry 2021-03-04 22:18:19 +0000
  • fafecb5f01 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Ross Thompson 2021-03-04 16:06:22 -0600
  • 106718b196 Remove rd2, working for non-compressed Jarred Allen 2021-03-04 16:46:43 -0500
  • 57e484cd55 Pipelined functional units for FPU Brett Mathis 2021-03-04 14:30:11 -0600
  • 3303a013ef Merge branch 'walker' into main Thomas Fleming 2021-03-04 15:27:03 -0500
  • 735c6789ea busybear: comment out instraccessfaultf for imem for now Noah Boorstin 2021-03-04 20:26:41 +0000
  • 1fb50aff6b Add reference output for mmu test Thomas Fleming 2021-03-04 15:17:49 -0500
  • 827dfd774b Merge branch 'main' into busybear Noah Boorstin 2021-03-04 20:16:03 +0000
  • 66e84f3a2c Merge branch 'bp' into main Concerns: 1. I don't think the correct data buses are going to the multiplier. 2. I'm not sure the FlushF signal is correct. Ross Thompson 2021-03-04 13:35:46 -0600
  • 4d14c714a7 Fixed forwarding around the 2 bit predictor. Ross Thompson 2021-03-04 13:01:41 -0600
  • 7347b3e1b7 Fix some constants in virtual memory test Thomas Fleming 2021-03-04 13:19:55 -0500
  • 246dbd05e7 fixed bugs Shreya Sanghai 2021-03-04 12:59:45 -0500
  • f0ec365117 added performance counters Shreya Sanghai 2021-03-04 11:40:18 -0500
  • 448cba2a5b JALR testing bbracker 2021-03-04 10:37:30 -0500
  • d98c69c4c6 changed test maker to output trace files for debug bbracker 2021-03-04 10:36:04 -0500
  • 52d95d415f Converted to using the BTB to predict the instruction class. Ross Thompson 2021-03-04 09:23:35 -0600
  • 554d529723 Slightly modified exe2memfile.pl script Teo Ene 2021-03-04 07:51:25 -0600
  • 06be82fc67 Added stop to coremark_bare testbench Teo Ene 2021-03-04 07:47:07 -0600
  • 8f1584ca04 Edited assemby of bare-metal coremark to make it run Teo Ene 2021-03-04 07:45:40 -0600
  • 396dc61564 Linux CoreMark and baremetal CoreMark split into two separate tests/configs Teo Ene 2021-03-04 07:44:33 -0600
  • 6ebb79abe0 Linux CoreMark is operational Teo Ene 2021-03-04 05:58:18 -0600
  • de3f2547f4 Install dtlb in dmem Thomas Fleming 2021-03-04 03:30:06 -0500
  • 1df7151fb6 Install tlb into ifu Thomas Fleming 2021-03-04 03:11:34 -0500
  • 2e409f2299 Merge branch 'tlb_toy' into main Thomas Fleming 2021-03-04 02:41:11 -0500
  • 5f98c932bf Move tlb into mmu directory Thomas Fleming 2021-03-04 02:39:08 -0500
  • f060f6cb9d Fix to 32-bit option of commit babe6ce9db Teo Ene 2021-03-04 01:33:34 -0600
  • 08a7f6ec25 In the process of updating coremark.RV64I program to work with Dr. Harris's perl script. Commiting to make it easier to switch branches Teo Ene 2021-03-04 01:27:05 -0600
  • d9f396ee0e Merge branch 'main' into tlb_toy Thomas Fleming 2021-03-04 01:18:04 -0500
  • 347275e7ee Generalize tlb module Thomas Fleming 2021-03-04 01:13:31 -0500
  • 6031269de8 Implemented fix disucssed with Elizabeth Teo Ene 2021-03-03 18:17:53 -0600
  • 394051c02f Begin hardware page table walker Thomas Fleming 2021-03-03 17:13:45 -0500
  • d8ac9034b7 Create virtual memory ad-hoc test Thomas Fleming 2021-03-03 17:06:37 -0500
  • 4562c61af3 Fix to last push Teo Ene 2021-03-03 15:20:38 -0600
  • 37bf3d836f Updated coremark .do file for easier debugging Teo Ene 2021-03-03 15:10:39 -0600
  • e6044b9867 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Teo Ene 2021-03-02 17:23:44 -0600
  • e7f7f980b3 Updated coremark .do file for easier debugging Teo Ene 2021-03-02 17:23:39 -0600
  • 21b1c4163c busybear: add sim-busybear and sim-busybear-batch based on sim-wally Noah Boorstin 2021-03-01 21:01:15 +0000
  • 62b441f3f5 busybear: probably discovered bug in ahb code Noah Boorstin 2021-03-01 20:56:04 +0000
  • 965d48afe7 busybear: only check pc when it actually changes Noah Boorstin 2021-03-01 19:08:35 +0000
  • 4833b36535 busybear: more adapting to new memory system Noah Boorstin 2021-03-01 18:50:42 +0000
  • 26d4024b33 busybear: fix bootram range Noah Boorstin 2021-03-01 17:45:21 +0000
  • 9bcddfa5dd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-03-01 00:09:55 -0500
  • 2543c29839 Initial (untested) implementation of lr and sc David Harris 2021-03-01 00:09:45 -0500
  • babe6ce9db Properly implemented the fix from commit 31c07b2adc Teo Ene 2021-02-28 22:22:04 -0600
  • e4bda37354 Merge branch 'main' into busybear Noah Boorstin 2021-02-28 20:48:23 +0000
  • 1858c32e9d add .nfs* files to gitignore Noah Boorstin 2021-02-28 20:48:01 +0000
  • bcc0010498 Merge branch 'main' into busybear Noah Boorstin 2021-02-28 20:45:08 +0000
  • f306d2d2e1 busybear: start preloading bootmem Noah Boorstin 2021-02-28 20:43:57 +0000
  • db86d20d11 busybear: check instead of providing InstrF Noah Boorstin 2021-02-28 16:46:53 +0000
  • a03796a519 busybear: change sstatus, mstatus reset value Noah Boorstin 2021-02-28 16:19:03 +0000
  • 6e70ae8b3d busybear: add 2nd dtim for bootram Noah Boorstin 2021-02-28 16:08:54 +0000
  • edd5e9106d busybear: remove gpio, start adding 2nd ram Noah Boorstin 2021-02-28 06:02:40 +0000
  • e5e345d161 busybear: instantiate normal wallypipelinedsoc Noah Boorstin 2021-02-28 06:02:21 +0000
  • 7592a0dacb Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data. Ross Thompson 2021-02-26 20:12:27 -0600
  • 37e6a45d76 Updating the test bench to include a function radix. Not done. Ross Thompson 2021-02-26 19:43:40 -0600
  • cf03afa880 Eliminated flushing pipeline on CSR reads David Harris 2021-02-26 17:00:07 -0500
  • c7863d58cd merged with main to integrate with AHB kaveh pezeshki 2021-02-26 05:37:10 -0800
  • ab9247d625 busybear: add main ram loading, better instr checking also Noah Boorstin 2021-02-26 20:26:54 +0000
  • ad631ec3a1 fixed sensitivity list on error checking always block, removed useless once and for all kaveh Pezeshki 2021-02-26 13:41:16 -0500
  • 015b632eb1 Cleaned out unused signals David Harris 2021-02-26 09:17:36 -0500
  • d32421822c restored kaveh pezeshki 2021-02-26 02:22:08 -0800
  • b16846bddb Clean up bus interface code David Harris 2021-02-26 01:03:47 -0500
  • 24f767a404 Retimed peripherals for AHB interface David Harris 2021-02-26 00:55:41 -0500
  • 4e6caf64d9 Fcmp/Fsgn pipeline modules Brett Mathis 2021-02-25 18:22:30 -0600
  • c060e427f0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-02-25 15:49:38 -0500
  • a16fd95eed Restored to working multiplier after Lab 2 David Harris 2021-02-25 15:32:43 -0500
  • ec82453ba1 FPU Assembly tests Brett Mathis 2021-02-25 14:32:36 -0600
  • 6be5bb1f84 Fixed previous commit Teo Ene 2021-02-25 11:24:44 -0600
  • 31c07b2adc Edited imem to account for TIMBASE==0; still hard-coded and needs to be improved, but works with coremark config now. Teo Ene 2021-02-25 11:23:01 -0600
  • 61b872a3e8 Changed TIMBASE in coremark config file Teo Ene 2021-02-25 11:03:41 -0600
  • 544df9e18c Merge remote-tracking branch 'origin/lab3' into main Teo Ene 2021-02-25 10:28:20 -0600
  • c47872c2af Changed .do file back to run all Teo Ene 2021-02-25 09:58:54 -0600
  • d00d42cf9a Merged bus into main David Harris 2021-02-25 00:28:41 -0500
  • 3b6807368f removed WALLY ALU tests to avoid merge conflict with main branch David Harris 2021-02-25 00:15:22 -0500
  • 3e5de35fc4 Added provisional coremark files from work with Elizabeth Teo Ene 2021-02-24 20:07:07 -0600
  • 3bb8e0d918 condensed always blocks to avoid race conditions kaveh pezeshki 2021-02-24 11:35:28 -0800
  • 3d82ceffb7 busybear: preload bootram Noah Boorstin 2021-02-24 18:44:50 +0000
  • f5e9c91193 All tests passing with bus interface David Harris 2021-02-24 07:25:03 -0500
  • b36a5614b4 added comments for RAM and bootram, removed trailing whitepace kaveh pezeshki 2021-02-23 21:28:33 -0800
  • c8e9edcc43 busybear: add bootram section in the same manner as ram Noah Boorstin 2021-02-24 02:02:28 +0000
  • a24270c4ca busybear: add support for subwords in ram Noah Boorstin 2021-02-24 01:51:18 +0000
  • 00605864fc busybear: start adding ram Noah Boorstin 2021-02-23 22:01:23 +0000