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Commit Graph

  • 694badcc6b Created tlbcontrol module to hide details David Harris 2021-07-06 03:25:11 -0400
  • f805aea236 Implemented TSR, TW, TVM, MXR status bits David Harris 2021-07-06 01:32:05 -0400
  • 8b23162d6d Fixed adrdecs to use Access signals for TIMs David Harris 2021-07-05 23:42:58 -0400
  • 71711c54c9 Don't generate HPTW when MEM_VIRTMEM=0 David Harris 2021-07-05 23:35:44 -0400
  • 179c8d3ed4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-07-05 23:23:17 -0400
  • 6bac566bb7 Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0 David Harris 2021-07-05 20:35:31 -0400
  • 530ddd667b Fixed combo loop in the page table walker. Ross Thompson 2021-07-05 16:37:26 -0500
  • 2a62ee2e70 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-07-05 16:07:27 -0500
  • 20cd0e208b added new mmu tests to makefrag and commented out in the testbench Kip Macsai-Goren 2021-07-05 10:54:30 -0400
  • 97b0c8f368 added final mmu test that passes make. They still don't pass simulation. Kip Macsai-Goren 2021-07-05 10:49:23 -0400
  • ec1df3f1e8 cleaned up comments, minor edits Kip Macsai-Goren 2021-07-05 10:47:20 -0400
  • 71978a144e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-07-05 10:45:44 -0400
  • 5f91b339aa Added F_SUPPORTED flag to disable floating point unit when not in MISA David Harris 2021-07-05 10:30:46 -0400
  • ac163e091c Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported David Harris 2021-07-04 19:33:46 -0400
  • 004cac91e1 Simplified PLIC with generate David Harris 2021-07-04 19:17:15 -0400
  • 0aae58abed Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb David Harris 2021-07-04 19:02:56 -0400
  • 600e7802dd Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb David Harris 2021-07-04 18:56:30 -0400
  • db5a06beaf Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-07-04 18:55:24 -0400
  • b23192cf1b Gave names to for loops in generate blocks for ease of reference David Harris 2021-07-04 18:52:16 -0400
  • 287935c09d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-07-04 18:17:16 -0400
  • 07f2064c19 Touched up TLB D and A bit checks David Harris 2021-07-04 18:17:09 -0400
  • ceac0352f7 ICacheCntrl now reacts differently to InstrPageFaultF vs ITLBWriteF bbracker 2021-07-04 18:17:06 -0400
  • b2c5c3f637 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-07-04 17:07:57 -0500
  • b0f199b574 Fixed TLB_ENTRIES merge conflict and handling of global PTEs David Harris 2021-07-04 18:05:22 -0400
  • 02721c29dc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-07-04 16:54:31 -0500
  • 17f37f21ff Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-07-04 16:53:16 -0500
  • 8b707f7703 Added ASID & Global PTE handling to TLB CAM David Harris 2021-07-04 17:53:08 -0400
  • 80666f0a71 Added ASID & Global PTE handling to TLB CAM David Harris 2021-07-04 17:52:00 -0400
  • a252416535 Removed the TranslationVAdrQ as it is not necessary. Ross Thompson 2021-07-04 16:49:34 -0500
  • 7191c03282 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-07-04 17:20:55 -0400
  • 9c84ab436a for GPIO give priority to clearing interrupts bbracker 2021-07-04 17:20:16 -0400
  • 1131ec8e35 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-07-04 16:19:42 -0500
  • 7f62808544 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-07-04 16:19:39 -0500
  • c110fffe69 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-07-04 17:15:40 -0400
  • 07ef67e537 Restructured TLB Read as AND-OR operation with one-hot match/read line David Harris 2021-07-04 17:01:22 -0400
  • 8337d6df68 Reorganized TLB to use one-hot read/write select signals to eliminate decoders and encoders David Harris 2021-07-04 16:33:13 -0400
  • e505510918 comment out rv64 virtual memory test so that tests make successfully bbracker 2021-07-04 16:16:59 -0400
  • c281539f36 TLB cleanup David Harris 2021-07-04 14:59:04 -0400
  • 5b70eb86b0 relocated lsuarb and pagetable walker inside the lsu. Does not pass busybear or buildroot, but passes rv32ic and rv64ic. Ross Thompson 2021-07-04 13:49:38 -0500
  • 81742ef9e2 TLB cleanup David Harris 2021-07-04 14:37:53 -0400
  • b2a003d9ac Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-07-04 14:31:01 -0400
  • 152923e552 TLB minor organization David Harris 2021-07-04 14:30:56 -0400
  • c9364b8840 Revert "Make Wally take InstrPageFaultF traps" bbracker 2021-07-04 13:31:30 -0400
  • 7e22ae973e Fixed MPRV and MXR checks in TLB David Harris 2021-07-04 13:20:29 -0400
  • 1b39481a16 TLB mux and swizzling cleanup David Harris 2021-07-04 12:53:52 -0400
  • 35210fd5f7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-07-04 12:48:20 -0400
  • 7db2be6dad Make Wally take InstrPageFaultF traps bbracker 2021-07-04 12:48:13 -0400
  • 735f3b4217 Replaced generates with arrays in TLB David Harris 2021-07-04 12:32:27 -0400
  • 67e191c6f3 Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries David Harris 2021-07-04 11:39:59 -0400
  • ccd9c05303 Switched to array notation for pmpchecker David Harris 2021-07-04 10:51:56 -0400
  • d6d66decf3 sv48 test makes as well, does not pass regression Kip Macsai-Goren 2021-07-04 01:59:18 -0400
  • 56650bbd3b Name Change, clean up on lots of comments, Kip Macsai-Goren 2021-07-04 01:58:54 -0400
  • accbebfa6f Commented out some unused modules David Harris 2021-07-04 01:40:27 -0400
  • e90c532258 Merge conflict on linux-waves.do David Harris 2021-07-04 01:22:10 -0400
  • 9645b023c9 Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang. David Harris 2021-07-04 01:19:38 -0400
  • d68791a6d9 optionally output GDB-formatted instruction list to main buildroot folder bbracker 2021-07-03 17:25:19 -0400
  • 9f16d08d0d removed mmustall and finished port annotations on ptw and lsuArb. Ross Thompson 2021-07-03 16:06:09 -0500
  • 043f1e10c5 Added explicit names to lsu, lsuarb and pagetable walker to make the code refactoring process eaiser. Ross Thompson 2021-07-03 15:51:25 -0500
  • 9566daccaa Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-07-03 16:32:27 -0400
  • 2524e05765 mmu test fully compiles and produces correct ovpsim outputs. regression is as of yet untested. Kip Macsai-Goren 2021-07-03 16:32:04 -0400
  • d8facacef6 src/cache/ICacheCntrl.sv Ben Bracker 2021-07-03 11:24:41 -0500
  • eff5a1b90f fix ICache indenting Ben Bracker 2021-07-03 11:11:07 -0500
  • 1fa4abf7b6 Changed IMMU ExecuteAccessF to 1 rather than InstrReadF to fix buildroot; simplified PMP checker David Harris 2021-07-03 03:29:33 -0400
  • d44916dacf Cleaned up PMA/PMP checker unused code David Harris 2021-07-03 02:25:31 -0400
  • 59b177beac stop busybear from hanging Ben Bracker 2021-07-02 17:22:09 -0500
  • 0bd18ff662 Fixed PMPCFG read faults David Harris 2021-07-02 17:08:13 -0400
  • cf688bd3f6 Fixed up the physical address generation for 64 bit page table walker. Ross Thompson 2021-07-02 15:49:32 -0500
  • 8e3149517a Fixed up the bit widths on the page table walker for rv32. Ross Thompson 2021-07-02 15:45:05 -0500
  • 7b3716c281 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-07-02 13:56:49 -0500
  • 20d6e57aa5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Katherine Parry 2021-07-02 12:56:53 -0400
  • 308c9ccaac FPU update - missing files Katherine Parry 2021-07-02 12:53:05 -0400
  • dbd33465e1 Merge branch 'main' into bigbadbranch Ross Thompson 2021-07-02 11:52:26 -0500
  • 5b6ebd7935 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-07-02 12:52:20 -0400
  • 30ff212ca8 FPU update Katherine Parry 2021-07-02 12:40:58 -0400
  • 76a43eb468 Optimized PMP checker logic and added support for configurable number of PMP registers David Harris 2021-07-02 11:05:25 -0400
  • c85e0df1ff Optimized PMP checker logic and added support for configurable number of PMP registers David Harris 2021-07-02 11:04:13 -0400
  • d1a366472f reverted change to the imperas tests order. Accidently commited change which placed the virtual memory tests first. Ross Thompson 2021-07-01 18:04:43 -0500
  • 118dfa9cec added page table walker fault exit for icache. Ross Thompson 2021-07-01 17:59:55 -0500
  • 61027f650c OMG. It's working! Ross Thompson 2021-07-01 17:37:53 -0500
  • 6916784354 Fixed tab space issue. Ross Thompson 2021-07-01 17:17:53 -0500
  • 2dc349ea6f Fixed the wrong virtual address write into the dtlb. Ross Thompson 2021-07-01 16:55:16 -0500
  • 70a15afe2e Correct physical implementation flow path Teo Ene 2021-07-01 16:37:49 -0500
  • ec21126474 Flow updated for 90nm Teo Ene 2021-07-01 13:32:42 -0500
  • 88a18496cf Got some stores working in virtual memory. Ross Thompson 2021-07-01 12:49:09 -0500
  • 157b1b31bf Icache ITLB interlock fix. Ross Thompson 2021-06-30 19:24:59 -0500
  • 002c32d2ad The icache ptw interlock is actually correct now. There needed to be a 1 cycle delay. Ross Thompson 2021-06-30 17:02:36 -0500
  • 9ec624702d Major rewrite of ptw to remove combo loop. Ross Thompson 2021-06-30 16:25:03 -0500
  • b2d8ba6742 The icache now correctly interlocks with the PTW on TLB miss. Ross Thompson 2021-06-30 11:24:26 -0500
  • dd84f2958e Page table walker now walks the table. Added interlock so the icache stalls. Page table walker not walking correctly, goes to fault state. Ross Thompson 2021-06-29 22:33:57 -0500
  • 0c2b7a1132 FPU control signals changed and FMA works Katherine Parry 2021-06-28 18:53:58 -0400
  • bc9c944ba0 Don't use this branch walker still broken. Ross Thompson 2021-06-28 17:26:11 -0500
  • 751e606fb7 trying out Noah and Kaveh's proposed hack for which CSRs to update for QEMU MMU bug bbracker 2021-06-26 08:30:58 -0400
  • c93b6abed2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-06-26 08:29:37 -0400
  • 17afd9e5e8 temporarily disable PMP checking for EBU accesses. bbracker 2021-06-26 07:19:51 -0400
  • 74833dc68c split intermediate GDB output file into smaller files for better debug experience bbracker 2021-06-26 07:18:26 -0400
  • d80ebab941 AMO and LR/SC instructions now working correctly. Page table walking is not working. Ross Thompson 2021-06-25 15:42:07 -0500
  • 12eff2bc5f Updated timing functions to read from MTIME register, TICKS_PER_SEC set to 10000 so timer reads millisecs Abe 2021-06-25 16:42:03 -0400
  • 2ab29c74f2 Fixed Coremark Score output printing. Also made it so that the loop that sets the iteration count increments iterations by 1 instead by increasing it by a factor of 10 each time (which was overkill for the timing that's needed to exit the loop) Abe 2021-06-25 16:27:23 -0400
  • 57a7074800 Some progress. Had to change how the page table walker got it's ready. Ross Thompson 2021-06-25 15:07:41 -0500
  • b4a788c341 Working through a combo loop. Ross Thompson 2021-06-25 14:49:27 -0500