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Make Wally take InstrPageFaultF traps

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bbracker 2021-07-04 12:48:13 -04:00
parent d68791a6d9
commit 7db2be6dad
3 changed files with 7 additions and 7 deletions
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4
wally-pipelined/src/ifu/ifu.sv
View File

@ -151,7 +151,7 @@ module ifu (
icache icache(.*,
.PCNextF(PCNextFPhys),
.PCPF(PCPFmmu),
.WalkerInstrPageFaultF(WalkerInstrPageFaultF));
.WalkerInstrPageFaultF);
flopenl #(32) AlignedInstrRawDFlop(clk, reset | reset_q, ~StallD, FlushD ? nop : FinalInstrRawF, nop, InstrRawD);
@ -184,7 +184,7 @@ module ifu (
assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
flopenl #(`XLEN) pcreg(clk, reset, ~StallF & ~ICacheStallF, PCNextF, `RESET_VECTOR, PCF);
flopenl #(`XLEN) pcreg(clk, reset, (~StallF & ~ICacheStallF) | WalkerInstrPageFaultF, PCNextF, `RESET_VECTOR, PCF);
// branch and jump predictor
generate

8
wally-pipelined/src/privileged/trap.sv
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@ -30,7 +30,7 @@ module trap (
input logic clk, reset,
input logic InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM,
input logic BreakpointFaultM, LoadMisalignedFaultM, StoreMisalignedFaultM,
input logic LoadAccessFaultM, StoreAccessFaultM, EcallFaultM, InstrPageFaultM,
input logic LoadAccessFaultM, StoreAccessFaultM, EcallFaultM, InstrPageFaultF,
input logic LoadPageFaultM, StorePageFaultM,
input logic mretM, sretM, uretM,
input logic [1:0] PrivilegeModeW, NextPrivilegeModeM,
@ -69,7 +69,7 @@ module trap (
assign BusTrapM = LoadAccessFaultM | StoreAccessFaultM;
assign NonBusTrapM = InstrMisalignedFaultM | InstrAccessFaultM | IllegalInstrFaultM |
LoadMisalignedFaultM | StoreMisalignedFaultM |
InstrPageFaultM | LoadPageFaultM | StorePageFaultM |
InstrPageFaultF | LoadPageFaultM | StorePageFaultM |
BreakpointFaultM | EcallFaultM |
InterruptM;
assign TrapM = BusTrapM | NonBusTrapM;
@ -121,7 +121,7 @@ module trap (
else if (PendingIntsM[9]) CauseM = (1 << (`XLEN-1)) + 9; // Supervisor External Int
else if (PendingIntsM[1]) CauseM = (1 << (`XLEN-1)) + 1; // Supervisor Sw Int
else if (PendingIntsM[5]) CauseM = (1 << (`XLEN-1)) + 5; // Supervisor Timer Int
else if (InstrPageFaultM) CauseM = 12;
else if (InstrPageFaultF) CauseM = 12;
else if (InstrAccessFaultM) CauseM = 1;
else if (InstrMisalignedFaultM) CauseM = 0;
else if (IllegalInstrFaultM) CauseM = 2;
@ -148,7 +148,7 @@ module trap (
if (InstrMisalignedFaultM) NextFaultMtvalM = InstrMisalignedAdrM;
else if (LoadMisalignedFaultM) NextFaultMtvalM = MemAdrM;
else if (StoreMisalignedFaultM) NextFaultMtvalM = MemAdrM;
else if (InstrPageFaultM) NextFaultMtvalM = PCM;
else if (InstrPageFaultF) NextFaultMtvalM = PCM;
else if (LoadPageFaultM) NextFaultMtvalM = MemAdrM;
else if (StorePageFaultM) NextFaultMtvalM = MemAdrM;
else if (IllegalInstrFaultM) NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM};

2
wally-pipelined/src/wally/wallypipelinedhart.sv
View File

@ -179,7 +179,7 @@ module wallypipelinedhart
ifu ifu(.InstrInF(InstrRData),
.WalkerInstrPageFaultF(WalkerInstrPageFaultF),
.WalkerInstrPageFaultF,
.*); // instruction fetch unit: PC, branch prediction, instruction cache
ieu ieu(.*); // integer execution unit: integer register file, datapath and controller