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  • d78e31e9df Forgot to include one hot decoder. Ross Thompson 2021-07-14 15:46:52 -0500
  • f4295ff097 Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts. This solves the committedM issue. Ross Thompson 2021-07-14 15:00:33 -0500
  • 335afb14e7 testvector unlinker for dev purposes bbracker 2021-07-14 11:05:34 -0400
  • e6d19be87c put back for now to test fdiv James Stine 2021-07-14 06:48:29 -0500
  • 782344cfd9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Abe 2021-07-14 04:47:31 -0400
  • ac92823c8d Commented out remaining ehitoa function declaration/calls and related char buff instances. Also commented out extra libraries not currently in use Abe 2021-07-14 04:46:11 -0400
  • 46e704b7ef Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-07-14 00:21:39 -0400
  • 92899b33f8 make testvector scripts agree with new file structure; use symbols to determine end of linux boot bbracker 2021-07-14 00:21:29 -0400
  • 9b756d6a94 Implemented uncached reads. Ross Thompson 2021-07-13 23:03:09 -0500
  • e8bf502bc2 Added CommitedM to data cache output. Ross Thompson 2021-07-13 22:43:42 -0500
  • 28887bb3d5 needed to create a directory for gdb script bbracker 2021-07-13 19:39:57 -0400
  • 3e57c899a2 Partially working changes to support uncached memory access. Not sure what CommitedM is. Ross Thompson 2021-07-13 17:24:59 -0500
  • 9f9b38db9f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Abe 2021-07-13 18:22:36 -0400
  • 9d83566637 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-07-13 17:41:47 -0400
  • 46001fef27 mod 2 of fpdivsqrt update James E. Stine 2021-07-13 16:59:17 -0400
  • 8382a17969 Update fpdivsqrt item until move into uarch James E. Stine 2021-07-13 16:53:20 -0400
  • f2bf4920d7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-07-13 16:16:04 -0400
  • 64d22753b5 changed QEMU to use different ports bbracker 2021-07-13 16:15:51 -0400
  • baa2b5d15f Fixed interaction between icache stall and dcache. On hit dcache needs to enter a cpu busy state when the cpu is stalled. Ross Thompson 2021-07-13 14:51:42 -0500
  • 3c1a717399 Fixed the fetch buffer accidental overwrite on eviction. Ross Thompson 2021-07-13 14:21:29 -0500
  • 32f27cfecf Dcache AHB address generation was wrong. Needed to zero the offset. Ross Thompson 2021-07-13 14:19:04 -0500
  • afc1bc9c38 Moved StoreStall into the hazard unit instead of in the d cache. Ross Thompson 2021-07-13 13:20:50 -0500
  • 9de97c1e20 Fixed busybear by restoring InstrValidW needed by testbench David Harris 2021-07-13 14:17:36 -0400
  • 47e16f5629 Fixed back to back store issue. Note there is a bug in the lsuarb which needs to arbitrate a few execution stage signals. Ross Thompson 2021-07-13 12:46:20 -0500
  • 46e1a008c3 Downloaded clean version of Coremark from EEMBC github page with which to benchmark RISCV-Wally Abe 2021-07-13 13:37:40 -0400
  • 2ba82d1a5c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-07-13 13:26:51 -0400
  • 223086ac33 added or.sv David Harris 2021-07-13 13:26:40 -0400
  • ca19b2e215 Fixed writting MStatus FS bits Katherine Parry 2021-07-13 13:22:04 -0400
  • efdec72df1 Fixed writting MStatus FS bits Katherine Parry 2021-07-13 13:20:30 -0400
  • 93d6688c3c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-07-13 13:19:24 -0400
  • b5dddec858 Fixed InstrValid from W to M stage for CSR performance counters David Harris 2021-07-13 13:19:13 -0400
  • 3565580f40 updated buildroot make procedure to incorporate configs more robustly bbracker 2021-07-13 12:40:14 -0400
  • 224e3b2991 Fixed subword write. subword read should not feed into subword write. Ross Thompson 2021-07-13 11:21:44 -0500
  • 30b7c4436c restored rv64ic config back to full sized dtim. Ross Thompson 2021-07-13 11:18:54 -0500
  • 3951eb56f5 Modularized the shadow memory to reduce performance hit. Ross Thompson 2021-07-13 10:55:57 -0500
  • e594eb540d Got the shadow ram cache flush working. Ross Thompson 2021-07-13 10:03:47 -0500
  • 99587f58f7 whoops I accidentally made main.config into a symbolic link; now it is a source file bbracker 2021-07-13 11:00:01 -0400
  • fab906821a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-07-13 10:04:13 -0400
  • 4b615c1564 working config for a buildroot that boots bbracker 2021-07-13 10:04:09 -0400
  • 861ef5e1cb Replaced .or with or_rows structural code in MMU read circuitry for synthesis. David Harris 2021-07-13 09:32:02 -0400
  • 49f6eec579 Team work on solving the dcache data inconsistency problem. Ross Thompson 2021-07-12 23:46:32 -0500
  • ecc9b5006e Now updates the dtim with the dirty data in the dcache. Simulation is showing issues. It lookslike the cache is not evicting the correct data. Ross Thompson 2021-07-12 15:13:27 -0500
  • 1cc258ade1 Progress towards the test bench flush. Ross Thompson 2021-07-12 14:22:13 -0500
  • f3ac46df86 fcvt.sv cleanup Katherine Parry 2021-07-11 21:30:01 -0400
  • 36f59f3c99 Almost all convert instructions pass Imperas tests Katherine Parry 2021-07-11 18:06:33 -0400
  • 6bd0ca673c rootfs.cpio no longer overlaps bbracker 2021-07-11 05:11:12 -0400
  • f26d635614 Fixed the spurious AHB requests to address 0. Somehow by not having a default (else) in the fsm branch selection for STATE_READY in the d cache it was possible to take an invalid branch through the fsm. Ross Thompson 2021-07-10 22:34:47 -0500
  • fed7042fd9 Loads are working. There is a bug when the icache stalls 1 cycle before the d cache. Ross Thompson 2021-07-10 22:15:44 -0500
  • 60ed023734 Actually writes the correct data now on stores. Ross Thompson 2021-07-10 17:48:47 -0500
  • efe37ea079 Write miss with eviction works. Ross Thompson 2021-07-10 15:17:40 -0500
  • d65c01bc29 Write Hits and Write Misses without eviction are working correctly! The next step is to add eviction of dirty lines. Ross Thompson 2021-07-10 10:56:25 -0500
  • feaeeaf6ac greatly stripped down unused stuff in linux config bbracker 2021-07-10 11:53:35 -0400
  • 20f2a4e47c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-07-09 19:18:35 -0400
  • d3ab6b192a added missing tlbmixer.sv David Harris 2021-07-09 19:18:23 -0400
  • 3be73695e3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-07-09 18:56:28 -0400
  • 2a54f6f242 fix_mem.py bugfix bbracker 2021-07-09 18:56:17 -0400
  • b1ceeb40df Loads in modelsim, but the first store double does not function correctly. The write address is wrong so the cache is updated using the wrong address. I think this is do to the cycle latency of stores. We probably need extra muxes to select between MemPAdrM and MemPAdrW depending on if the write is a full cache block or a word write from the CPU. Ross Thompson 2021-07-09 17:14:54 -0500
  • 1f52a2f938 organize/update buildroot scripts for new image bbracker 2021-07-09 17:03:47 -0400
  • 4c0cee1c19 Design loads in modelsim, but trap is an X. Ross Thompson 2021-07-09 15:37:16 -0500
  • ec80cc1820 Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented. Also faults and the dcache ptw interlock are not implemented. Ross Thompson 2021-07-09 15:16:38 -0500
  • 0dff489de2 comment clean up to match textbook chapter Kip Macsai-Goren 2021-07-09 12:54:09 -0400
  • 39bd7e7edc Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-07-09 07:53:30 -0400
  • 5c2f774c35 Simplified tlbmixer mux to and-or David Harris 2021-07-08 23:34:24 -0400
  • 74b6d13195 Fixed missing stall in InstrRet counter David Harris 2021-07-08 20:08:04 -0400
  • 44a48cf28d organize linux-testgen folder, add readme to describe Buildroot process, add Buildroot config source files bbracker 2021-07-08 19:18:11 -0400
  • 94c3fde724 Renamed signal in LSU toLSU and fromLSU to toDCache and fromDCache. Ross Thompson 2021-07-08 18:03:52 -0500
  • 93aa39ca31 completed read miss branch through dcache fsm. The challenge now is to connect to ahb and lsu. Ross Thompson 2021-07-08 17:53:08 -0500
  • 4f1a85ca7c Eliminate reserved bits from TLB RAM David Harris 2021-07-08 17:35:00 -0400
  • 38772de21f Array of muxes in tlbmixer; abbreviated PPN and VPN to match diagram David Harris 2021-07-08 16:58:11 -0400
  • 1190729896 TLB cleanup to match diagrams David Harris 2021-07-08 16:52:06 -0400
  • 910ddb83ae This d cache fsm is getting complex. Ross Thompson 2021-07-08 15:26:16 -0500
  • 1fe06bc670 Partial implementation of the data cache. Missing the fsm. Ross Thompson 2021-07-07 17:52:16 -0500
  • 5d5274ec73 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-07-07 06:32:29 -0400
  • 2bab3f769b Renamed tlb ReadLines to Matches David Harris 2021-07-07 06:32:26 -0400
  • 84711fbdc8 Updated MISA defining as well as porting sizes for peripherals (34 to 56) Abe 2021-07-07 02:37:09 -0400
  • c721341691 Commented out printf statements for quicker simulation time. Also added function minstretDiff, which calculates the number of machine instructions retired during the coremark benchmark's runtime, excluding setup time. Abe 2021-07-07 02:28:11 -0400
  • b536065ee8 Removed debugging loop to test timers for clarity Abe 2021-07-06 23:37:43 -0400
  • 8dc40e988e Updated portme file to include counters MTIME and MINSTRET. Timer currently set to read milliseconds running at 100MHZ, but this can be changed by setting a different clock speed in the testbench sv file and manipulating TIMER_RES_DIVIDER on line 120 Abe 2021-07-06 23:35:47 -0400
  • b757c96b2d Changed SvMode to SVMode on line 76 Abe 2021-07-06 23:28:58 -0400
  • af619dcd75 Added ASID matching for CAM David Harris 2021-07-06 18:56:25 -0400
  • 8350622f65 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-07-06 18:54:41 -0400
  • 7d857cf4bd more TLB name touchups David Harris 2021-07-06 18:39:30 -0400
  • e08a578908 fixed upper bits page fault signal Kip Macsai-Goren 2021-07-06 18:32:47 -0400
  • 2e2aa2a972 connected signals in tlb by name instead of .* David Harris 2021-07-06 17:22:10 -0400
  • ee3a321002 changed tlbphysicalpagemask to structural David Harris 2021-07-06 17:16:58 -0400
  • f960561cbb changed tlbphysicalpagemask to structural David Harris 2021-07-06 17:08:04 -0400
  • fd0cd930a7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-07-06 15:29:49 -0400
  • 032c38b7e7 MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB David Harris 2021-07-06 15:29:42 -0400
  • 757e4f3b54 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-07-06 15:05:51 -0400
  • 412691df2d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-07-06 13:45:20 -0500
  • 3345ed7ff4 Merged several of the load/store/instruction access faults inside the mmu. Still need to figure out what is wrong with the generation of load page fault when dtlb hit. Ross Thompson 2021-07-06 13:43:53 -0500
  • d3dd70e3e6 more completely uncomment MMU tests to make sim wally work bbracker 2021-07-06 14:33:52 -0400
  • 137145144f edited tests so regression would pass with float enabled. this IS NOT a comprehensive test for fs yet Kip Macsai-Goren 2021-07-06 14:28:26 -0400
  • 8854532a79 Disabled MCOUNTINHIBIT to enable csr counters (changed to 32'h0 on line 140) Abe 2021-07-06 12:37:58 -0400
  • 7af8cfba18 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-07-06 10:41:45 -0500
  • 6e7e318396 Fixed bug in the LSU pagetable walker interlock. Ross Thompson 2021-07-06 10:41:36 -0500
  • b4082ba776 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-07-06 10:44:17 -0400
  • 30fdd7abc8 Cleaned up tlb output muxing David Harris 2021-07-06 10:44:05 -0400
  • d58cad89a8 Replaced muxing of upper address bits with disregarding their match. Moved WriteEnables gate into tlblru to eliminate WriteLines David Harris 2021-07-06 10:38:30 -0400
  • 7e9961cac4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main Kip Macsai-Goren 2021-07-06 10:16:34 -0400