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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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This commit is contained in:
Kip Macsai-Goren 2021-07-06 15:05:51 -04:00
commit 757e4f3b54
8 changed files with 37 additions and 37 deletions
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10
wally-pipelined/src/ifu/ifu.sv
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@ -81,7 +81,8 @@ module ifu (
input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0],
output logic PMPInstrAccessFaultF, PMAInstrAccessFaultF,
output logic InstrAccessFaultF,
output logic ISquashBusAccessF
// output logic [5:0] IHSELRegionsF
@ -100,6 +101,8 @@ module ifu (
logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
logic PMPInstrAccessFaultF, PMAInstrAccessFaultF;
logic PMALoadAccessFaultM, PMAStoreAccessFaultM;
logic PMPLoadAccessFaultM, PMPStoreAccessFaultM; // *** these are just so that the mmu has somewhere to put these outputs, they're unused in this stage
// if you're allowed to parameterize outputs/ inputs existence, these are an easy delete.
@ -117,7 +120,7 @@ module ifu (
endgenerate
mmu #(.TLB_ENTRIES(`ITLB_ENTRIES), .IMMU(1))
itlb(.VirtualAddress(PCF),
immu(.VirtualAddress(PCF),
.Size(2'b10),
.PTE(PageTableEntryF),
.PageTypeWriteVal(PageTypeF),
@ -132,7 +135,8 @@ module ifu (
.ReadAccessM(1'b0),
.WriteAccessM(1'b0),
.SquashBusAccess(ISquashBusAccessF),
// .HSELRegions(IHSELRegionsF),
.LoadAccessFaultM(),
.StoreAccessFaultM(),
.DisableTranslation(1'b0),
.*);

6
wally-pipelined/src/lsu/lsu.sv
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@ -94,9 +94,6 @@ module lsu
input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0], // *** this one especially has a large note attached to it in pmpchecker.
output logic PMALoadAccessFaultM, PMAStoreAccessFaultM,
output logic PMPLoadAccessFaultM, PMPStoreAccessFaultM, // *** can these be parameterized? we dont need the m stage ones for the immu and vice versa.
output logic DSquashBusAccessM
// output logic [5:0] DHSELRegionsM
@ -235,6 +232,7 @@ module lsu
.ReadAccessM(MemRWMtoLSU[1]),
.SquashBusAccess(DSquashBusAccessM),
.DisableTranslation(DisableTranslation),
.InstrAccessFaultF(),
// .SelRegions(DHSELRegionsM),
.*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist?
@ -268,9 +266,7 @@ module lsu
// Determine if address is valid
assign LoadMisalignedFaultM = DataMisalignedMfromLSU & MemRWMtoLSU[1];
assign LoadAccessFaultM = MemRWMtoLSU[1];
assign StoreMisalignedFaultM = DataMisalignedMfromLSU & MemRWMtoLSU[0];
assign StoreAccessFaultM = MemRWMtoLSU[0];
// Handle atomic load reserved / store conditional
generate

15
wally-pipelined/src/mmu/mmu.sv
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@ -63,15 +63,14 @@ module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries
// Faults
output logic TLBPageFault,
output logic InstrAccessFaultF, LoadAccessFaultM, StoreAccessFaultM,
// PMA checker signals
input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,
input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
output logic SquashBusAccess, // *** send to privileged unit
output logic PMPInstrAccessFaultF, PMPLoadAccessFaultM, PMPStoreAccessFaultM,
output logic PMAInstrAccessFaultF, PMALoadAccessFaultM, PMAStoreAccessFaultM
output logic SquashBusAccess // *** send to privileged unit
// output logic [5:0] SelRegions
);
@ -80,6 +79,11 @@ module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries
logic Cacheable, Idempotent, AtomicAllowed; // *** here so that the pmachecker has somewhere to put these outputs. *** I'm leaving them as outputs to pma checker, but I'm stopping them here.
// Translation lookaside buffer
logic PMAInstrAccessFaultF, PMPInstrAccessFaultF;
logic PMALoadAccessFaultM, PMPLoadAccessFaultM;
logic PMAStoreAccessFaultM, PMPStoreAccessFaultM;
// only instantiate TLB if Virtual Memory is supported
generate
if (`MEM_VIRTMEM) begin
@ -105,6 +109,9 @@ module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries
pmpchecker pmpchecker(.*);
assign SquashBusAccess = PMASquashBusAccess || PMPSquashBusAccess;
assign SquashBusAccess = PMASquashBusAccess | PMPSquashBusAccess;
assign InstrAccessFaultF = PMAInstrAccessFaultF | PMPInstrAccessFaultF;
assign LoadAccessFaultM = PMALoadAccessFaultM | PMPLoadAccessFaultM;
assign StoreAccessFaultM = PMAStoreAccessFaultM | PMPStoreAccessFaultM;
endmodule

1
wally-pipelined/src/privileged/csrm.sv
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@ -171,6 +171,7 @@ module csrm #(parameter
// verilator lint_off WIDTH
logic [5:0] entry;
always_comb begin
entry = '0;
IllegalCSRMAccessM = !(`S_SUPPORTED | `U_SUPPORTED & `N_SUPPORTED) &&
(CSRAdrM == MEDELEG || CSRAdrM == MIDELEG); // trap on DELEG register access when no S or N-mode
if (CSRAdrM >= PMPADDR0 && CSRAdrM < PMPADDR0 + `PMP_ENTRIES) // reading a PMP entry

17
wally-pipelined/src/privileged/privileged.sv
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@ -60,11 +60,11 @@ module privileged (
// *** do these need to be split up into one for dmem and one for ifu?
// instead, could we only care about the instr and F pins that come from ifu and only care about the load/store and m pins that come from dmem?
input logic PMAInstrAccessFaultF, PMPInstrAccessFaultF,
input logic PMALoadAccessFaultM, PMPLoadAccessFaultM,
input logic PMAStoreAccessFaultM, PMPStoreAccessFaultM,
input logic InstrAccessFaultF,
input logic LoadAccessFaultM,
input logic StoreAccessFaultM,
output logic IllegalFPUInstrE,
output logic IllegalFPUInstrE,
output logic [1:0] PrivilegeModeW,
output logic [`XLEN-1:0] SATP_REGW,
output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
@ -87,8 +87,7 @@ module privileged (
logic IllegalFPUInstrM;
logic LoadPageFaultM, StorePageFaultM;
logic InstrPageFaultF, InstrPageFaultD, InstrPageFaultE, InstrPageFaultM;
logic InstrAccessFaultF, InstrAccessFaultD, InstrAccessFaultE, InstrAccessFaultM;
logic LoadAccessFaultM, StoreAccessFaultM;
logic InstrAccessFaultD, InstrAccessFaultE, InstrAccessFaultM;
logic IllegalInstrFaultM, TrappedSRETM;
logic BreakpointFaultM, EcallFaultM;
@ -159,14 +158,12 @@ module privileged (
// A page fault might occur because of insufficient privilege during a TLB
// lookup or a improperly formatted page table during walking
// *** merge these at the lsu level.
assign InstrPageFaultF = ITLBInstrPageFaultF || WalkerInstrPageFaultF;
assign LoadPageFaultM = DTLBLoadPageFaultM || WalkerLoadPageFaultM;
assign StorePageFaultM = DTLBStorePageFaultM || WalkerStorePageFaultM;
assign InstrAccessFaultF = PMAInstrAccessFaultF || PMPInstrAccessFaultF;
assign LoadAccessFaultM = PMALoadAccessFaultM || PMPLoadAccessFaultM;
assign StoreAccessFaultM = PMAStoreAccessFaultM || PMPStoreAccessFaultM;
// pipeline fault signals
flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD,
{InstrPageFaultF, InstrAccessFaultF},

3
wally-pipelined/src/privileged/trap.sv
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@ -66,6 +66,7 @@ module trap (
// Trigger Traps and RET
// Created groups of trap signals so that bus could take in all traps it doesn't already produce (i.e. using just TrapM to squash access created circular paths)
// *** Ben July 06, 2021 probably remove bus and nonbus trapm after dcache implemenation.
assign BusTrapM = LoadAccessFaultM | StoreAccessFaultM;
assign NonBusTrapM = InstrMisalignedFaultM | InstrAccessFaultM | IllegalInstrFaultM |
LoadMisalignedFaultM | StoreMisalignedFaultM |
@ -153,4 +154,4 @@ module trap (
else if (StorePageFaultM) NextFaultMtvalM = MemAdrM;
else if (IllegalInstrFaultM) NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM};
else NextFaultMtvalM = 0;
endmodule
endmodule

10
wally-pipelined/src/wally/wallypipelinedhart.sv
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@ -33,7 +33,6 @@ module wallypipelinedhart
// input logic [31:0] InstrF,
// Privileged
input logic TimerIntM, ExtIntM, SwIntM,
input logic InstrAccessFaultF,
input logic DataAccessFaultM,
input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT,
// Bus Interface
@ -119,9 +118,6 @@ module wallypipelinedhart
logic [1:0] PageTypeF, PageTypeM;
// PMA checker signals
logic PMPInstrAccessFaultF, PMPLoadAccessFaultM, PMPStoreAccessFaultM;
logic PMAInstrAccessFaultF, PMALoadAccessFaultM, PMAStoreAccessFaultM;
logic DSquashBusAccessM, ISquashBusAccessF;
var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0];
var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0];
@ -170,6 +166,8 @@ module wallypipelinedhart
logic StallWtoLSU;
logic StallWfromLSU;
logic [2:0] SizeFromLSU;
logic InstrAccessFaultF;
ifu ifu(.InstrInF(InstrRData),
@ -235,10 +233,6 @@ module wallypipelinedhart
.LoadAccessFaultM(LoadAccessFaultM), // connects to privilege
.StoreMisalignedFaultM(StoreMisalignedFaultM), // connects to privilege
.StoreAccessFaultM(StoreAccessFaultM), // connects to privilege
.PMALoadAccessFaultM(PMALoadAccessFaultM),
.PMAStoreAccessFaultM(PMAStoreAccessFaultM),
.PMPLoadAccessFaultM(PMPLoadAccessFaultM),
.PMPStoreAccessFaultM(PMPStoreAccessFaultM),
// connected to hptw. Move to internal.
.PCF(PCF),

12
wally-pipelined/testbench/testbench-imperas.sv
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@ -44,14 +44,14 @@ module testbench();
logic [31:0] InstrW;
logic [`XLEN-1:0] meminit;
string tests32mmu[] = '{
//string tests32mmu[] = '{
//"rv32mmu/WALLY-MMU-SV32", "3000"
};
// };
string tests64mmu[] = '{
//string tests64mmu[] = '{
//"rv64mmu/WALLY-MMU-SV48", "3000",
//"rv64mmu/WALLY-MMU-SV39", "3000"
};
//};
string tests32f[] = '{
@ -540,7 +540,7 @@ string tests32f[] = '{
else tests = {tests, tests64iNOc};
if (`M_SUPPORTED) tests = {tests, tests64m};
if (`A_SUPPORTED) tests = {tests, tests64a};
if (`MEM_VIRTMEM) tests = {tests, tests64mmu};
//if (`MEM_VIRTMEM) tests = {tests, tests64mmu};
if (`F_SUPPORTED) tests = {tests64f, tests};
if (`D_SUPPORTED) tests = {tests64d, tests};
end
@ -558,7 +558,7 @@ string tests32f[] = '{
if (`M_SUPPORTED % 2 == 1) tests = {tests, tests32m};
if (`F_SUPPORTED) tests = {tests32f, tests};
if (`A_SUPPORTED) tests = {tests, tests32a};
if (`MEM_VIRTMEM) tests = {tests, tests32mmu};
//if (`MEM_VIRTMEM) tests = {tests, tests32mmu};
end
end
end