93 Commits

Author	SHA1	Message	Date
Noah Boorstin	edd5e9106d	busybear: remove gpio, start adding 2nd ram	2021-02-28 06:02:40 +00:00
Noah Boorstin	e5e345d161	busybear: instantiate normal wallypipelinedsoc	2021-02-28 06:02:21 +00:00
kaveh pezeshki	c7863d58cd	merged with main to integrate with AHB	2021-02-26 05:37:10 -08:00
David Harris	015b632eb1	Cleaned out unused signals	2021-02-26 09:17:36 -05:00
David Harris	b16846bddb	Clean up bus interface code	2021-02-26 01:03:47 -05:00
David Harris	24f767a404	Retimed peripherals for AHB interface	2021-02-26 00:55:41 -05:00
David Harris	c060e427f0	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-02-25 15:49:38 -05:00
David Harris	a16fd95eed	Restored to working multiplier after Lab 2	2021-02-25 15:32:43 -05:00
Brett Mathis	ec82453ba1	FPU Assembly tests	2021-02-25 14:32:36 -06:00
Teo Ene	6be5bb1f84	Fixed previous commit	2021-02-25 11:24:44 -06:00
Teo Ene	31c07b2adc	Edited imem to account for TIMBASE==0; still hard-coded and needs to be improved, but works with coremark config now.	2021-02-25 11:23:01 -06:00
David Harris	d00d42cf9a	Merged bus into main	2021-02-25 00:28:41 -05:00
David Harris	f5e9c91193	All tests passing with bus interface	2021-02-24 07:25:03 -05:00
Katherine Parry	8f5cc19143	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-02-23 20:21:53 +00:00
Katherine Parry	7b103423e1	inital FMA push	2021-02-23 20:19:12 +00:00
Noah Boorstin	ceb7df3561	busybear: instantiate soc instead of hart	2021-02-23 18:59:06 +00:00
David Harris	c52a99ce2d	Fixed fetch stall after jump in bus unit	2021-02-23 09:08:57 -05:00
David Harris	817f81c356	Debugging Bus interface	2021-02-22 13:48:30 -05:00
kaveh pezeshki	62d9185212	Merge remote-tracking branch 'origin/tlb_toy' into busybear	2021-02-22 02:23:01 -08:00
Thomas Fleming	21552eaf9d	Create simple TLB ... This TLB is just a demonstration and is not currently instantiated by the IFU or DFU.	2021-02-18 18:06:09 -05:00
David Harris	acd7ba8b60	Updated creation date of mul	2021-02-18 08:13:08 -05:00
David Harris	2f5b4c3a25	Resotred part of multiplier for lab 2	2021-02-17 16:14:04 -05:00
David Harris	64536dbc34	Removed multiplier for lab 2	2021-02-17 16:06:16 -05:00
David Harris	dc758a0c7b	Multiplier tweaks	2021-02-17 16:00:27 -05:00
David Harris	3edf910c18	Started to integrate OSU divider	2021-02-17 15:38:44 -05:00
David Harris	cb0054b524	Multiply instructions working	2021-02-17 15:29:20 -05:00
Noah Boorstin	5835641c6c	busybear testbench: check (almost) all the CSRs	2021-02-16 20:03:24 -05:00
David Harris	8dec69c2ce	Added MUL	2021-02-15 22:27:35 -05:00
David Harris	37dba8fd26	More memory interface, ALU testgen	2021-02-15 10:10:50 -05:00
bbracker	9231646fb3	bus rw bugfix and peripherals testing	2021-02-12 00:02:45 -05:00
David Harris	183a2dcfb5	Debugging bus interface.	2021-02-10 01:43:54 -05:00
David Harris	2357f5513b	Debugging instruction fetch	2021-02-09 11:02:17 -05:00
David Harris	63c7c18771	Fixed lw by delaying read value by one cycle	2021-02-07 23:28:21 -05:00
David Harris	3551cc859b	Data memory bus integration	2021-02-07 23:21:55 -05:00
Noah Boorstin	14cde0d59c	Change CSR reset and available bits to conform to OVPsim ... Now actually keeping perfectly in line with OVP for the first 100k instrs. Yay.	2021-02-04 22:03:45 +00:00
Brett Mathis	79cb7ed571	Parallel FSR's and F CTRL logic	2021-02-04 02:25:55 -06:00
David Harris	91f6858de7	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-02-02 19:44:43 -05:00
David Harris	a44c2abb12	Minor tweaks	2021-02-02 19:44:37 -05:00
Noah Boorstin	00d9e13d68	same thing but do that right this time	2021-02-02 21:47:15 +00:00
Noah Boorstin	56ff32f857	change undefined syntax in extend.sv ... don't need verilator execption anymore	2021-02-02 21:39:20 +00:00
David Harris	d56d7a75a6	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00
David Harris	aee44bb343	Changed DTIM latency to 2 cycles	2021-02-02 14:22:12 -05:00
David Harris	4fbb5f0f1b	Cleaned up hazard interface	2021-02-02 13:53:13 -05:00
David Harris	c23afbda3a	Moved LoadStall generation to IEU	2021-02-02 13:42:23 -05:00
David Harris	aad1d3d7dd	Moved writeback pipeline registers from datapth into DMEM and CSR	2021-02-02 13:02:31 -05:00
David Harris	9d7e242596	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
Brett Mathis	94de3e9fb2	OSU FPU IP initial commit	2021-02-01 19:33:43 -06:00
David Harris	056b147b13	Renamed DCU to DMEM	2021-02-01 18:52:22 -05:00
David Harris	396cea1ea7	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00
David Harris	fc1fb94217	Working on reading instruction from TIM	2021-01-30 01:57:51 -05:00