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737 Commits

Author SHA1 Message Date
Katherine Parry
77ea4e47cb removed minus 1 case in rounding 2022-07-13 15:01:38 -07:00
Katherine Parry
26e39dd325 removed the +1 in the cvt 2022-07-13 09:41:35 -07:00
Katherine Parry
e05b2a07d2 removed warnings and took a mux out of the critical path 2022-07-12 18:32:17 -07:00
Katherine Parry
452b017f9a found the bug in the store modification 2022-07-12 22:42:19 +00:00
Katherine Parry
2ada8a8bc1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-12 22:37:20 +00:00
Katherine Parry
5c0ecfa433 forgot a file 2022-07-11 18:31:51 -07:00
Katherine Parry
7815b81716 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-11 18:30:29 -07:00
Katherine Parry
b728e5054d variable interations implemented in radix-4 divider 2022-07-11 18:30:21 -07:00
David Harris
2bc8ff555b added comment about checking SRAM size 2022-07-10 12:48:51 +00:00
David Harris
9cb675b2e4 added comment about RAMs in cacheway 2022-07-10 12:47:34 +00:00
Katherine Parry
ca4fe08fd9 renamed FLoad2 to FStore2 2022-07-09 00:26:45 +00:00
Katherine Parry
cd53ae67d9 moved fpu ieu write data mux to lsu 2022-07-08 23:56:57 +00:00
Katherine Parry
3476579e02 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-08 12:30:50 -07:00
Katherine Parry
9ef45f36fd renamed signals in cvt and prostproc 2022-07-08 12:30:43 -07:00
James Stine
c5dfefe669 Update SRAM to /proj/wally 2022-07-08 08:09:55 -05:00
David Harris
c72e4d43d2 erge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-08 09:09:07 +00:00
David Harris
381f3298d8 Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc 2022-07-08 09:09:02 +00:00
David Harris
1ce0975366 Adjusting byte writes to RAM 2022-07-08 08:45:21 +00:00
David Harris
3f9e662201 Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables 2022-07-08 08:44:37 +00:00
David Harris
9b6d9666c5 Removed unused swbytemask from CLINT 2022-07-08 08:43:24 +00:00
Katherine Parry
905b7ffc84 moved unsused division code again 2022-07-07 16:41:26 -07:00
Katherine Parry
2bbde827e6 Revert "moved old divsqrt to unusedsrc" 
This reverts commit c9f5ae12ea.
 2022-07-07 16:29:17 -07:00
Katherine Parry
c9f5ae12ea moved old divsqrt to unusedsrc 2022-07-07 16:09:56 -07:00
Katherine Parry
41c16be012 srt divider merged into fpu 2022-07-07 16:01:33 -07:00
David Harris
96a75d7749 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-07 22:00:59 +00:00
Katherine Parry
08769e35ae modified wally shared 2022-07-07 21:59:43 +00:00
David Harris
2f342c430e fixing port errors 2022-07-07 21:57:10 +00:00
Katherine Parry
0b40f38f02 added load and store test 2022-07-07 21:48:51 +00:00
David Harris
88e3233935 Preliminary SRAM integration 2022-07-07 19:56:20 +00:00
David Harris
08ae2db080 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-06 23:43:05 +00:00
Ross Thompson
bd46cf76a9 Fixed an issue with direct map cache's nextway logic. 
Also found a small error in the replacement policy.
 2022-07-06 18:34:30 -05:00
Madeleine Masser-Frye
cb33d2289b fixed width mismatch for rv64 ieuadrM and readdatawordM 2022-07-06 22:39:35 +00:00
David Harris
9ef38145d7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-06 13:26:26 +00:00
David Harris
a599084b88 PLIC and UART passing tests on APB 2022-07-06 13:26:14 +00:00
Madeleine Masser-Frye
846f12aa2e new priority onehot module for better area/time 2022-07-06 00:08:59 +00:00
Madeleine Masser-Frye
01e6d69a67 took first match out of pmpadrdec 2022-07-06 00:02:01 +00:00
Madeleine Masser-Frye
50e9b6ac53 fixed concatenation syntax 2022-07-05 22:36:54 +00:00
David Harris
d73645944f APB CLINT passing regression 2022-07-05 15:51:35 +00:00
David Harris
d033659beb Modified uncore to use AHB bridge to GPIO 2022-07-05 05:02:21 +00:00
David Harris
e7fe7ad0c8 AHB bridge for gpio 2022-07-05 05:01:59 +00:00
David Harris
4723ff559c Added reference to Schmookler01 for LOA 2022-07-05 05:01:12 +00:00
David Harris
aa3dc8bfe1 Added comments to PLIC about likely bug 2022-07-05 05:00:29 +00:00
David Harris
4c48d71e4b removed delay in ahblite 2022-07-05 04:59:28 +00:00
Katherine Parry
010a05f583 added missing files 2022-07-03 21:40:47 -07:00
Katherine Parry
1b4584e825 Renaming signals to match chapter 2022-07-03 12:26:22 -07:00
David Harris
bde1c5eb1b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-02 19:37:14 +00:00
David Harris
52dbc9f8be FMA ZAligned name 2022-07-02 19:35:13 +00:00
Katherine Parry
575b73fa8c some prostprocessing cleanup 2022-07-01 14:55:46 -07:00
Katherine Parry
6baded9121 added rv32 double precision stores - untested 2022-06-28 21:33:31 +00:00
Katherine Parry
f2d05911ca very basic early termination passes testfloat 64-bit tests 2022-06-28 00:16:22 +00:00
Katherine Parry
f25bb4a384 radix-4 early termination working for special cases - not working completely 2022-06-27 20:43:55 +00:00
Katherine Parry
2d5d1f4e8f radix-4 divider passing all double precision testfloat tests 2022-06-27 17:04:51 +00:00
Katherine Parry
06f7f9b147 fixed commented out error and removed killprod from result selection 2022-06-25 01:42:23 +00:00
Katherine Parry
d16ae7c305 passing regression again 2022-06-25 00:31:32 +00:00
Katherine Parry
913a381442 commented out error - also some divider bugs fixed 2022-06-25 00:04:53 +00:00
Katherine Parry
c1b4e7fd2c modified result select to account for x/inf 2022-06-24 21:23:15 +00:00
Katherine Parry
a65c0eb679 radix 4 division denormal result handeling 2022-06-24 21:02:50 +00:00
Katherine Parry
d058ec6329 added denormal input handeling - radix 4 2022-06-24 19:41:40 +00:00
Katherine Parry
fc75fc633f division by zero added 2022-06-24 01:09:44 +00:00
Katherine Parry
86cdbd90e6 forgot a file 2022-06-23 23:01:30 +00:00
Katherine Parry
97ded2cdd9 div debug - accounted for 1 bit normalization in exponent calculation 2022-06-23 22:59:43 +00:00
Katherine Parry
d17596353b lint warning fix 2022-06-23 22:37:44 +00:00
Katherine Parry
b54d84195f added radix-4 0/d handling 2022-06-23 22:36:19 +00:00
slmnemo
ded2631567 Removed big64.txt reference, fixing a warning 2022-06-23 14:39:53 -07:00
David Harris
2c4b86c703 Fixed typo in clint 2022-06-23 21:27:46 +00:00
David Harris
ceddc99ac9 Reset mtimecmp in clint 2022-06-23 21:20:55 +00:00
Katherine Parry
49067792dc fixt lint error 2022-06-23 16:11:50 +00:00
Katherine Parry
4a6dee5926 Testfloat running division - not passing 2022-06-23 00:07:34 +00:00
Madeleine Masser-Frye
0161683945 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-21 20:31:06 +00:00
Madeleine Masser-Frye
fe31ee92e8 switched comparator to dc flip version 2022-06-21 20:30:33 +00:00
Katherine Parry
254ebf478e added fld in rv32 - needs testing 2022-06-20 22:53:13 +00:00
Katherine Parry
93906b9457 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-15 22:58:42 +00:00
Katherine Parry
e121dcd4af postprocess out of fpu critical path 2022-06-15 22:58:33 +00:00
Madeleine Masser-Frye
c2493168b6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-15 18:30:27 +00:00
Madeleine Masser-Frye
76e30ed8ab cleanup, plots for paper 2022-06-15 18:28:36 +00:00
Katherine Parry
11b252a735 some synth fpu optimizations 2022-06-14 23:58:39 +00:00
Katherine Parry
998876ce49 removed false critical path from fpu 2022-06-14 16:50:46 +00:00
Katherine Parry
566001e07b fixed acciedental critical path in FPU 2022-06-14 00:02:38 +00:00
Katherine Parry
31fd8772cf postprocessing unit created and passing all tests 2022-06-13 22:47:51 +00:00
David Harris
8ea484a343 Cleanup on RAM module 2022-06-13 19:37:43 +00:00
David Harris
b7a7ca6eac Typo in gpio reset 2022-06-13 19:37:05 +00:00
slmnemo
915b8e2adb Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-13 12:27:23 -07:00
slmnemo
7b704f8db0 Merge branch 'cacheburstmode' into main. 
Cache burst mode is now working! It also uses the new RAM.
 2022-06-13 12:26:18 -07:00
slmnemo
98c07ce2c0 Added more comments 2022-06-13 12:26:08 -07:00
David Harris
ccd16210bc Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-13 19:26:07 +00:00
David Harris
e9ef9a5cb8 Fixed XOR logic in GPIO 2022-06-13 19:26:03 +00:00
slmnemo
3d715a098c Added comment about name of LSUBusInit/Lock signal 2022-06-13 10:56:02 -07:00
slmnemo
cadd62e49f Removed irrelevant comments in ahblite and made it more clear when to use certain transmission signals 2022-06-10 20:43:56 -07:00
slmnemo
beb4317e68 Added comments to signals added so the bus is easier to analyze 2022-06-10 20:30:04 -07:00
slmnemo
b7357efc6b Fixed failed regression state by only enabling counting when doing cached operations 2022-06-10 20:00:09 -07:00
slmnemo
63ed390c90 Fixed error where CntReset would be high one cycle too long, adding a cycle of delay. Broke wally64priv by failing trap-sret-01. 2022-06-10 19:10:01 -07:00
Madeleine Masser-Frye
422bd2043f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-10 21:11:47 +00:00
Madeleine Masser-Frye
7cdf9cd4d3 added 'd' suffix to muxes for data-critical synths 2022-06-10 21:11:05 +00:00
slmnemo
dc11066ff2 Passed Regression: Seems to work perfectly fine 2022-06-09 18:21:13 -07:00
slmnemo
ec7cdee0f3 Merge branch 'main' into cacheburstmode 2022-06-09 17:51:03 -07:00
slmnemo
5a6eae214a ? 2022-06-09 17:50:47 -07:00
slmnemo
3e8d3bae88 Changes made on 9th Jun 2022-06-09 17:33:51 -07:00
slmnemo
4ff105f18c Fixed lint error 2022-06-09 17:22:04 -07:00
David Harris
c836f37a08 New RAM for further testing 2022-06-09 23:50:43 +00:00
David Harris
dd4fa7c682 qslc_r4a2 generator 2022-06-09 17:26:47 +00:00
slmnemo
0d04751c77 Fixed error when doing uncached accesses where HTRANS was always 2 2022-06-08 18:58:07 -07:00
slmnemo
81d373c7ab Fixed error related to bus being unable to complete a line write after a memory read followed by an idle and cachewrite request. 2022-06-08 17:34:02 -07:00
Madeleine Masser-Frye
0e64494e46 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-09 00:08:15 +00:00
Madeleine Masser-Frye
a58a756076 added one bit muxes for data critical synths 2022-06-09 00:06:12 +00:00
slmnemo
11924bdd9b Fixed error where MEMREAD would go into INSTRREAD even when no INSTRREAD was pending 2022-06-08 15:59:15 -07:00
slmnemo
e17ee3073e Fixed ifu displaying LSU bus state in wave.do 2022-06-08 15:30:32 -07:00
slmnemo
315c2f0669 Working version: Fixed error where Word count would always increment even without AHB to bus ACK 2022-06-08 15:29:32 -07:00
slmnemo
054cf5f7b0 Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors 2022-06-08 15:03:15 -07:00
DTowersM
6402b2dec4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-06-08 16:28:18 +00:00
DTowersM
6944996329 added #1 delays to Stalls and Flushes in hazard unit 2022-06-08 16:28:09 +00:00
slmnemo
284e0395a0 Merge branch 'main' into cacheburstmode 2022-06-08 02:21:33 +00:00
slmnemo
2d76953d42 Added lock signal to ensure AHB speaks with the right bus 2022-06-08 02:19:21 +00:00
David Harris
5240bd1c90 Modified RAM for single-cycle latency 2022-06-08 02:06:00 +00:00
David Harris
3c8eafc8ee Cleaned bram interface 2022-06-08 01:39:44 +00:00
David Harris
9e5ab4d378 Added ahbapbbridge and cleaning RAM 2022-06-08 01:31:34 +00:00
slmnemo
6d36150c3d Fixed off-by-one error in busdp capture 2022-06-07 19:36:39 +00:00
slmnemo
73e0c1c07f Reworked bus to handle burst interfacing 2022-06-07 11:22:53 +00:00
Katherine Parry
8fa0fc4229 fma synth warnings and errors removed 2022-06-06 16:06:04 +00:00
Madeleine Masser-Frye
56a053fc3d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-03 21:08:49 +00:00
Madeleine Masser-Frye
31e9d0a41a added muxes and inv, fixed priority encoder 2022-06-03 21:03:13 +00:00
Katherine Parry
6b39b8c702 fixed compilation errors 2022-06-03 15:34:17 +00:00
Katherine Parry
03280c0f9c added createallvectors 2022-06-02 21:56:05 +00:00
Katherine Parry
9a09ee3a35 fpu paramaterized - except fdivsqrt 2022-06-02 19:50:28 +00:00
David Harris
1d8bc2dc1b Added stalls for pending SFENCE.VMA and FENCE.I in hazard unit 2022-06-02 09:37:59 -07:00
David Harris
faa15b1f8d Cleaned up comments in controller 2022-06-02 15:48:33 +00:00
David Harris
c7ec9282fe Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working. 2022-06-02 14:18:55 +00:00
Katherine Parry
e42afbfb30 paramerterized some small fma units 2022-06-01 23:34:29 +00:00
Katherine Parry
dd19e55b8f unpacker optimizations 2022-06-01 16:52:21 +00:00
slmnemo
446ad498aa Fixed double assignment on LSUBurstType 2022-06-01 01:04:49 +00:00
slmnemo
cf05fec9c7 Added signals to change HTRANS to the correct signal based on schematic as well as a way to tell if we are not on the first access 2022-05-31 16:33:05 -07:00
slmnemo
a86c4d5ff3 Merge branch 'cacheburstmode' of github.com:davidharrishmc/riscv-wally into cacheburstmode 2022-05-31 15:57:55 -07:00
slmnemo
9ad1a42886 Redid the FSM to prepare for burst mode implementation 2022-05-31 15:57:42 -07:00
David Harris
475a84491e Unpackinput cleanup 2022-05-31 22:31:21 +00:00
David Harris
f9533fea1a Removed normalized output from unpack and simplified interface 2022-05-31 21:32:31 +00:00
David Harris
0d0a9cba66 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-31 21:12:45 +00:00
David Harris
aa7b0616e4 ../src/privileged/csrc.sv 2022-05-31 21:12:17 +00:00
Katherine Parry
f6ac33ce8a reorginized unpackinput signals 2022-05-31 17:40:34 +00:00
Katherine Parry
4ed7933aa3 added unpackinput.sv 2022-05-31 16:18:50 +00:00
David Harris
788fe406b5 Moved delegation logic from privmode to trap to simplify interface 2022-05-31 14:58:11 +00:00
David Harris
0cfe9e3373 Removed unused fp add and convert modules 2022-05-29 23:07:56 +00:00
Katherine Parry
950a17bef5 fixed lint error 2022-05-28 10:20:13 -07:00
slmnemo
f78fa3b9b9 Reverted incorrect Ack 2022-05-28 10:06:26 +00:00
David Harris
b04e9ac1f6 fixed merge conflicts 2022-05-28 09:44:55 +00:00
David Harris
4237bb7abd Added comments to some files, added a+b = 0 detector to comparator.sv 2022-05-28 09:41:48 +00:00
Katherine Parry
9c58c63864 removed unused signal from FMA 2022-05-27 16:47:56 -07:00
Katherine Parry
a0ff98042c unpacker adds 1 to denorm expoents 2022-05-27 14:37:10 -07:00
Katherine Parry
95b506c5e0 some optimizations in unpacker 2022-05-27 11:36:04 -07:00
Katherine Parry
1be91753fe moved lzc to generic and small optimizations on fcvt 2022-05-27 09:04:02 -07:00
Katherine Parry
c6d79cd718 Removed guard bit from fma rounding 2022-05-27 08:23:46 -07:00
slmnemo
bc17f883d4 changed ahb FSM and caught potential bug in ack/wordcountthreshold when on last word 2022-05-26 18:41:27 -07:00