Ross Thompson
|
0bfbcef8ab
|
Now past the CLINT issues.
|
2021-08-06 16:16:39 -05:00 |
|
Ross Thompson
|
9be10cdc8b
|
Partial conversion of the linux trace checking to read in the file in the Memory Stage so it is possible to overwrite registers, memory, and interrupts.
|
2021-08-06 16:06:50 -05:00 |
|
Ross Thompson
|
c749d08542
|
fixed the read timer issue but we still have problems with interrupts and i/o devices.
|
2021-08-06 10:16:06 -05:00 |
|
Ross Thompson
|
3582be4dbb
|
Fixed issue with desync of PCW and ExpectedPCW in linux test bench. The ERROR macro had a 10 ns delay which caused the trace to skip 1 instruction.
|
2021-08-05 16:49:03 -05:00 |
|
Ross Thompson
|
f808b29065
|
Added some comments to linux testbench.
|
2021-07-30 17:57:03 -05:00 |
|
Ross Thompson
|
e166cc84ee
|
Patched up changes for wally-pipelined.do and wally-buildroot.do to support moved common testbench files.
|
2021-07-30 14:24:50 -05:00 |
|
Ross Thompson
|
74fba4bb06
|
Moved the test bench modules to a common directory.
|
2021-07-30 14:16:14 -05:00 |
|
Ross Thompson
|
d8878581f4
|
Created new linux test bench and parsing scripts.
|
2021-07-29 20:26:50 -05:00 |
|
Kip Macsai-Goren
|
3008111bcd
|
added tests for 64/32 bit pma/pmp checker. They compile, but skip OVPsim simulation. They DO NOT pass regression yet
|
2021-07-23 16:02:42 -04:00 |
|
Kip Macsai-Goren
|
381a93b45b
|
added sfence to legal instructions, zeroed out rom file to populate for tests
|
2021-07-23 15:55:08 -04:00 |
|
Kip Macsai-Goren
|
da9ead2d95
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-07-23 15:16:01 -04:00 |
|
bbracker
|
0e64b99dc0
|
testbench workaround for QEMU's SSTATUS XLEN bits
|
2021-07-23 14:00:44 -04:00 |
|
Kip Macsai-Goren
|
52faa22774
|
include SFENCE.VMA in legal instructions
|
2021-07-22 20:24:24 -04:00 |
|
David Harris
|
21a65f45cd
|
Partial work on Unpacking exponents to larger word size. FCVT and FMA are presently broken.
|
2021-07-22 14:18:27 -04:00 |
|
bbracker
|
cca16cc5b4
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-07-21 20:07:03 -04:00 |
|
bbracker
|
6e460c5032
|
replace physical address checking with virtual address checking because address translator is broken
|
2021-07-21 19:47:13 -04:00 |
|
Katherine Parry
|
01f0b4e5df
|
FDIV and FSQRT work
|
2021-07-21 14:08:14 -04:00 |
|
Katherine Parry
|
b9081e514c
|
FMA parameterized
|
2021-07-20 22:04:21 -04:00 |
|
bbracker
|
f9b6bd91f5
|
fix PC checking during InstrPageFault; fix order of S-mode CSR checking; rename peripheral scopes to not be genblk
|
2021-07-20 17:55:44 -04:00 |
|
bbracker
|
a02694a529
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-07-20 15:04:13 -04:00 |
|
bbracker
|
a3823ce3a9
|
commented out old hack that used hardcoded addresses
|
2021-07-20 15:03:55 -04:00 |
|
David Harris
|
e5e3f5abe6
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-07-20 14:46:58 -04:00 |
|
David Harris
|
1f3dfa20f6
|
flag for optional boottim
|
2021-07-20 14:46:37 -04:00 |
|
bbracker
|
6b72b1f859
|
ignore mhpmcounters because QEMU doesn't implement them
|
2021-07-20 13:37:52 -04:00 |
|
bbracker
|
a1ea654b11
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-07-20 12:08:46 -04:00 |
|
David Harris
|
e1a1a8395e
|
Parameterized I$/D$ configurations and added sanity check assertions in testbench
|
2021-07-20 08:57:13 -04:00 |
|
bbracker
|
9e658466e6
|
testbench hack to ignore MTVAL for illegal instr faults; testbench upgrade to not check PCW for illegal instr faults; testbench hack to not check speculative instrs following an MRET (it seems MRET has 1 stage more latency than a branch instr)
|
2021-07-20 05:40:39 -04:00 |
|
bbracker
|
3b10ea9785
|
major fixes to CSR checking
|
2021-07-20 00:22:07 -04:00 |
|
bbracker
|
c1d63fe77c
|
MemRWM shouldn't factor into PCD checking
|
2021-07-19 18:03:30 -04:00 |
|
bbracker
|
f7d040af1e
|
make testbench ignore MIP because of timing imprecision and because QEMU maybe isn't getting MTIP right anyways
|
2021-07-19 17:11:42 -04:00 |
|
bbracker
|
65df5c087b
|
adapt testbench to removal of ReadDataWEn signal
|
2021-07-19 15:42:14 -04:00 |
|
bbracker
|
ae5663a244
|
adapt testbench to removal of signal
|
2021-07-19 15:41:50 -04:00 |
|
bbracker
|
cd469035be
|
make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset
|
2021-07-19 15:13:03 -04:00 |
|
Katherine Parry
|
c9180f4ebd
|
FDIV and FSQRT passes when simulating in modelsim
|
2021-07-18 23:00:04 -04:00 |
|
bbracker
|
5e9dcb3f1c
|
linux testbench progress
|
2021-07-18 18:47:40 -04:00 |
|
Katherine Parry
|
60dabb9094
|
fdivsqrt inegrated, but not completley working
|
2021-07-18 14:03:37 -04:00 |
|
Ross Thompson
|
14220684b6
|
Fixed bug with rv32a/WALLY-LRSC test in imperas. Minor issue.
|
2021-07-17 21:02:24 -05:00 |
|
David Harris
|
8d348dacce
|
Started atomics
|
2021-07-17 21:11:41 -04:00 |
|
bbracker
|
82fc766819
|
swapped out linux testbench signal names
|
2021-07-17 14:48:12 -04:00 |
|
David Harris
|
87aa527de7
|
hptw: minor cleanup
|
2021-07-17 13:40:12 -04:00 |
|
David Harris
|
ef63e1ab52
|
hptw: factored pregen
|
2021-07-17 11:11:10 -04:00 |
|
David Harris
|
dac22d5016
|
Removed more unused signals from ahblite
|
2021-07-17 02:21:54 -04:00 |
|
Kip Macsai-Goren
|
d10fd25c33
|
included virtual memory tests in testbench
|
2021-07-16 17:57:24 -04:00 |
|
Ross Thompson
|
5e18a15a4c
|
Added guide for Ben to do linux conversion.
|
2021-07-16 15:04:30 -05:00 |
|
Ross Thompson
|
6521d2b468
|
Also changed the shadow ram's dcache copy widths.
Merge branch 'dcache' into main
|
2021-07-16 14:21:09 -05:00 |
|
Ross Thompson
|
e5d624c1fa
|
Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.
|
2021-07-15 11:56:35 -05:00 |
|
Ross Thompson
|
fa26aec588
|
Merge branch 'main' into dcache
|
2021-07-15 11:55:20 -05:00 |
|
Ross Thompson
|
b9902b0560
|
Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits.
|
2021-07-15 11:00:42 -05:00 |
|
Ross Thompson
|
704f4f724e
|
dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed.
|
2021-07-14 23:08:07 -05:00 |
|
Ross Thompson
|
ba1e1ec231
|
Finally have the ptw correctly walking through the dcache to update the itlb.
Still not working fully.
|
2021-07-14 22:26:07 -05:00 |
|
Katherine Parry
|
c74d26eea4
|
Fixed lint warning
|
2021-07-14 21:24:48 -04:00 |
|
Ross Thompson
|
2c946a282f
|
Fixed d cache not honoring StallW for uncache writes and reads.
|
2021-07-14 17:23:28 -05:00 |
|
Ross Thompson
|
e91501985c
|
Routed CommittedM and PendingInterruptM through the lsu arb.
|
2021-07-14 16:18:09 -05:00 |
|
Ross Thompson
|
3e57c899a2
|
Partially working changes to support uncached memory access. Not sure what CommitedM is.
|
2021-07-13 17:24:59 -05:00 |
|
Katherine Parry
|
efdec72df1
|
Fixed writting MStatus FS bits
|
2021-07-13 13:20:30 -04:00 |
|
Ross Thompson
|
3951eb56f5
|
Modularized the shadow memory to reduce performance hit.
|
2021-07-13 10:55:57 -05:00 |
|
Ross Thompson
|
e594eb540d
|
Got the shadow ram cache flush working.
|
2021-07-13 10:03:47 -05:00 |
|
Ross Thompson
|
49f6eec579
|
Team work on solving the dcache data inconsistency problem.
|
2021-07-12 23:46:32 -05:00 |
|
Ross Thompson
|
ecc9b5006e
|
Now updates the dtim with the dirty data in the dcache.
Simulation is showing issues. It lookslike the cache is not
evicting the correct data.
|
2021-07-12 15:13:27 -05:00 |
|
Ross Thompson
|
1cc258ade1
|
Progress towards the test bench flush.
|
2021-07-12 14:22:13 -05:00 |
|
Katherine Parry
|
36f59f3c99
|
Almost all convert instructions pass Imperas tests
|
2021-07-11 18:06:33 -04:00 |
|
bbracker
|
d3dd70e3e6
|
more completely uncomment MMU tests to make sim wally work
|
2021-07-06 14:33:52 -04:00 |
|
Kip Macsai-Goren
|
20cd0e208b
|
added new mmu tests to makefrag and commented out in the testbench
|
2021-07-05 10:54:30 -04:00 |
|
David Harris
|
5f91b339aa
|
Added F_SUPPORTED flag to disable floating point unit when not in MISA
|
2021-07-05 10:30:46 -04:00 |
|
David Harris
|
9645b023c9
|
Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
|
2021-07-04 01:19:38 -04:00 |
|
Ben Bracker
|
59b177beac
|
stop busybear from hanging
|
2021-07-02 17:22:09 -05:00 |
|
bbracker
|
13cf7c0934
|
linux testbench now ignores HWRITE glitches caused by flush glitches
|
2021-06-25 09:28:52 -04:00 |
|
bbracker
|
5b47da21ba
|
made testbench-linux's PCDwrong be FlushD
|
2021-06-25 08:15:19 -04:00 |
|
Katherine Parry
|
7e3483b283
|
FPU forwarding reworked pt.1
|
2021-06-24 18:39:18 -04:00 |
|
bbracker
|
13df69abdb
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-06-24 01:42:41 -04:00 |
|
bbracker
|
be962cb1ff
|
overhauled linux testbench and spoofed MTTIME interrupt
|
2021-06-24 01:42:35 -04:00 |
|
Katherine Parry
|
8eed89616c
|
fpu clean-up
|
2021-06-23 16:42:40 -04:00 |
|
Katherine Parry
|
353a27f12f
|
rv64f FLW passes imperas tests
|
2021-06-22 16:36:16 -04:00 |
|
David Harris
|
7930c2ebb4
|
Commented out 100k tests to improve speed
|
2021-06-21 01:43:18 -04:00 |
|
David Harris
|
1ec90a5e1f
|
Reversed [0:...] with [...:0] in bus widths across the project
|
2021-06-21 01:17:08 -04:00 |
|
bbracker
|
bf3c2dc089
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-06-20 22:29:40 -04:00 |
|
bbracker
|
3000c27acd
|
linux actually uses FPU now!
|
2021-06-20 22:29:21 -04:00 |
|
Katherine Parry
|
2b67f25683
|
all rv64f instructions except convert, divide, square root, and FLD pass
|
2021-06-20 20:24:09 -04:00 |
|
bbracker
|
2643130c41
|
read from MSTATUS workaround because QEMU has incorrect MSTATUS
|
2021-06-20 10:11:39 -04:00 |
|
bbracker
|
14ae87ff0a
|
testbench update b/c QEMU extends 32b CSRs to 64b
|
2021-06-20 09:24:19 -04:00 |
|
bbracker
|
c77aabdc6f
|
make buildroot ignore SSTATUS because QEMU did not originally log it
|
2021-06-20 05:31:24 -04:00 |
|
bbracker
|
918ff5093a
|
MSTATUS workaround
|
2021-06-20 04:48:09 -04:00 |
|
bbracker
|
069a79fafd
|
workaround for ignoring MTIME
|
2021-06-20 02:26:39 -04:00 |
|
bbracker
|
d62d9a7aac
|
make buildroot waves only turn on after a user-specified point
|
2021-06-20 00:39:30 -04:00 |
|
bbracker
|
8d242d73b5
|
fixed PCtext error by using blocking assignments
|
2021-06-18 17:37:40 -04:00 |
|
bbracker
|
03a45aeef1
|
restore graphical buildroot sim
|
2021-06-18 11:58:16 -04:00 |
|
bbracker
|
faae30c31c
|
remove unused testbench-busybear.sv
|
2021-06-18 08:15:19 -04:00 |
|
David Harris
|
35c74348a4
|
allow all size memory access in CLINT; added underscore to peripheral address symbols
|
2021-06-18 08:05:50 -04:00 |
|
David Harris
|
336936cc39
|
Cleaned up name of MTIME register in CSRC
|
2021-06-18 07:53:49 -04:00 |
|
bbracker
|
5b96f7fbd7
|
making linux waveforms more useful
|
2021-06-17 08:37:37 -04:00 |
|
bbracker
|
b459d0cc80
|
changed parsedCSRs2] to parsedCSRs
|
2021-06-17 05:18:14 -04:00 |
|
David Harris
|
01d6ca1e2a
|
Fixed lint WIDTH errors
|
2021-06-09 20:58:20 -04:00 |
|
David Harris
|
b613f46c2d
|
Resized BOOT TIM to 1 KB
|
2021-06-08 14:04:32 -04:00 |
|
bbracker
|
cc91c774a6
|
Ah big ole merge! Passes sim-wally-batch and linting, so should be fine
|
2021-06-08 12:41:25 -04:00 |
|
bbracker
|
e7e4105931
|
* GPIO comprehensive testing
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
|
2021-06-08 12:32:46 -04:00 |
|
Kip Macsai-Goren
|
c96695b1b6
|
implemented simpler page mixers, cleaned up a bit
|
2021-06-07 18:32:34 -04:00 |
|
David Harris
|
2ae5ca19b5
|
Continued merge
|
2021-06-07 12:49:47 -04:00 |
|
David Harris
|
ff62000e2c
|
Second attept to commit refactoring config files
|
2021-06-07 12:37:46 -04:00 |
|
David Harris
|
dc0b19dfaa
|
Merge difficulties
|
2021-06-07 09:50:23 -04:00 |
|
David Harris
|
d5ec797ba4
|
Refactored configuration files and renamed testbench-busybear to testbench-linux
|
2021-06-07 09:46:52 -04:00 |
|