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226 Commits

Author SHA1 Message Date
bbracker
11d4a8ab34 first pass at PLIC interface 2021-03-22 10:14:21 -04:00
Katherine Parry
f741ba7702 fixed various bugs in the FMA 2021-03-21 22:53:04 +00:00
Katherine Parry
e317e7511e messy FMA rewrite using section 7.5.4 in The Handbook of Floating-Point Arithmetic 2021-03-20 02:05:16 +00:00
bbracker
85363e941d AHB bugfixes and sim waveview refactoring 2021-03-18 18:25:12 -04:00
Shreya Sanghai
bbe0957df5 Merge branch 'gshare' into main 
Conflicts:
	wally-pipelined/regression/wave.do
 2021-03-18 17:25:48 -04:00
Ross Thompson
1091dd10c1 Switched to gshare from global history. 
Fixed a few minor bugs.
 2021-03-18 16:05:59 -05:00
Ross Thompson
8f4051543c Fixed minor bug with the size of gshare. 2021-03-18 16:00:09 -05:00
Shreya Sanghai
eb86bfc084 removed unnecesary PC registers in ifu 2021-03-18 16:31:21 -04:00
Thomas Fleming
8d484174a7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-18 14:36:42 -04:00
Thomas Fleming
7f7597e667 Connect tlb, pagetablewalker, and memory 2021-03-18 14:35:46 -04:00
Noah Boorstin
bc1a0c6ee7 change ifndef to generate/if 2021-03-18 12:50:19 -04:00
Noah Boorstin
a2b0af460e everyone gets a bootram 2021-03-18 12:35:37 -04:00
Shreya Sanghai
36f0631203 added gshare and global history predictor 2021-03-16 17:03:01 -04:00
Shreya Sanghai
9eed875886 added global history branch predictor 2021-03-16 16:06:40 -04:00
Shreya Sanghai
08e9149e20 made performance counters count branch misprediction 2021-03-16 11:24:17 -04:00
Shreya Sanghai
74f1641c5a Merge branch 'counters' into main 
added a configurable number of performance counters
 2021-03-16 11:01:30 -04:00
bbracker
345254b5a3 slightly smarter dtim HREADY 2021-03-13 06:55:34 -05:00
bbracker
c5015e5809 imem rd2 adrbits bugfix 2021-03-13 00:10:41 -05:00
bbracker
f4fb546969 clint HREADY signal update 2021-03-12 20:23:55 -05:00
Ross Thompson
6ee97830f7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-12 14:58:04 -06:00
Ross Thompson
7743d8edc3 Cleanup of the branch predictor flush and stall controls. 2021-03-12 14:57:53 -06:00
David Harris
865c103599 64-bit AMO debugged 2021-03-11 23:18:33 -05:00
Thomas Fleming
1294235837 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/ahblite.sv
 2021-03-11 00:15:58 -05:00
David Harris
42275e92ed Initial untested implementation of AMO instructions 2021-03-11 00:11:31 -05:00
Noah Boorstin
2c25e270a2 change flop in ahb controller to use normal flop module 2021-03-10 19:14:02 +00:00
David Harris
17c0f9629a WALLY-LRSC atomic test passing 2021-03-09 09:28:25 -05:00
David Harris
9c7da510fb Created atomic test vector and directories 2021-03-08 09:38:55 -05:00
Ross Thompson
87ed6d510c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-05 15:27:22 -06:00
Ross Thompson
301166d062 Oups. I forgot to update other do files with the commands to preload the branch predictor memories. 2021-03-05 15:23:53 -06:00
Thomas Fleming
be6ee84d87 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-05 15:46:51 -05:00
Noah Boorstin
86142e764a Merge branch 'main' into busybear 2021-03-05 20:27:19 +00:00
bbracker
850a2e9329 added a delay to sel signals 2021-03-05 15:07:34 -05:00
bbracker
77e2e357a7 more merging fixes 2021-03-05 14:36:07 -05:00
bbracker
ed4ff1ecd0 remove deprecated mem signals 2021-03-05 14:27:38 -05:00
bbracker
0f4a231543 first merge of ahb fix 2021-03-05 14:24:22 -05:00
Thomas Fleming
2e2eb5839f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-05 13:35:44 -05:00
Thomas Fleming
8c97143be6 Place tlb parameters into constant header file 2021-03-05 13:35:24 -05:00
Thomas Fleming
7e11317a2d Export SATP_REGW from csrs to MMU modules 2021-03-05 01:22:53 -05:00
Noah Boorstin
f48af209c4 busybear: make CSRs only weird for us 2021-03-05 00:46:32 +00:00
Ross Thompson
a662aa487c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-04 17:31:27 -06:00
Noah Boorstin
dfae278ffb busybear: make imperas tests work again 2021-03-04 22:44:49 +00:00
Katherine Parry
cfac6bf0c7 fixed various bugs 2021-03-04 22:20:39 +00:00
Katherine Parry
09564f1c77 fixed various bugs 2021-03-04 22:20:28 +00:00
Katherine Parry
a6bc39b5ad fixed various bugs 2021-03-04 22:20:23 +00:00
Katherine Parry
526e3f5996 fixed various bugs 2021-03-04 22:20:02 +00:00
Katherine Parry
1e906b36a0 fixed various bugs 2021-03-04 22:19:21 +00:00
Katherine Parry
3fb0f323b8 fixed various bugs 2021-03-04 22:18:47 +00:00
Katherine Parry
fdfc0dbf46 fixed various bugs 2021-03-04 22:18:19 +00:00
Thomas Fleming
3303a013ef Merge branch 'walker' into main 2021-03-04 15:27:03 -05:00
Noah Boorstin
735c6789ea busybear: comment out instraccessfaultf for imem for now 2021-03-04 20:26:41 +00:00
Noah Boorstin
827dfd774b Merge branch 'main' into busybear 
Conflicts:
	wally-pipelined/src/uncore/imem.sv
 2021-03-04 20:16:03 +00:00
Ross Thompson
66e84f3a2c Merge branch 'bp' into main 
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
 2021-03-04 13:35:46 -06:00
Ross Thompson
4d14c714a7 Fixed forwarding around the 2 bit predictor. 2021-03-04 13:01:41 -06:00
Shreya Sanghai
246dbd05e7 fixed bugs 2021-03-04 12:59:45 -05:00
Shreya Sanghai
f0ec365117 added performance counters 2021-03-04 11:42:52 -05:00
Ross Thompson
52d95d415f Converted to using the BTB to predict the instruction class. 2021-03-04 09:23:35 -06:00
Thomas Fleming
de3f2547f4 Install dtlb in dmem 2021-03-04 03:30:06 -05:00
Thomas Fleming
1df7151fb6 Install tlb into ifu 2021-03-04 03:11:34 -05:00
Thomas Fleming
2e409f2299 Merge branch 'tlb_toy' into main 2021-03-04 02:41:11 -05:00
Thomas Fleming
5f98c932bf Move tlb into mmu directory 2021-03-04 02:39:08 -05:00
Teo Ene
f060f6cb9d Fix to 32-bit option of commit babe6ce9db 2021-03-04 01:33:34 -06:00
Thomas Fleming
d9f396ee0e Merge branch 'main' into tlb_toy 2021-03-04 01:18:04 -05:00
Thomas Fleming
347275e7ee Generalize tlb module 
- number of tlb entries is now parameterized
- tlb now supports rv64i
 2021-03-04 01:13:31 -05:00
Thomas Fleming
394051c02f Begin hardware page table walker 2021-03-03 17:13:45 -05:00
Noah Boorstin
62b441f3f5 busybear: probably discovered bug in ahb code 2021-03-01 20:56:04 +00:00
Noah Boorstin
4833b36535 busybear: more adapting to new memory system 2021-03-01 18:50:42 +00:00
Noah Boorstin
26d4024b33 busybear: fix bootram range 2021-03-01 17:45:21 +00:00
David Harris
9bcddfa5dd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-01 00:09:55 -05:00
David Harris
2543c29839 Initial (untested) implementation of lr and sc 2021-03-01 00:09:45 -05:00
Teo Ene
babe6ce9db Properly implemented the fix from commit 31c07b2adc 2021-02-28 22:22:04 -06:00
Noah Boorstin
bcc0010498 Merge branch 'main' into busybear 2021-02-28 20:45:08 +00:00
Noah Boorstin
f306d2d2e1 busybear: start preloading bootmem 2021-02-28 20:43:57 +00:00
Noah Boorstin
a03796a519 busybear: change sstatus, mstatus reset value 2021-02-28 16:19:03 +00:00
Noah Boorstin
6e70ae8b3d busybear: add 2nd dtim for bootram 2021-02-28 16:08:54 +00:00
Noah Boorstin
edd5e9106d busybear: remove gpio, start adding 2nd ram 2021-02-28 06:02:40 +00:00
Noah Boorstin
e5e345d161 busybear: instantiate normal wallypipelinedsoc 2021-02-28 06:02:21 +00:00
Ross Thompson
7592a0dacb Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data. 2021-02-26 20:12:27 -06:00
David Harris
cf03afa880 Eliminated flushing pipeline on CSR reads 2021-02-26 17:00:07 -05:00
David Harris
015b632eb1 Cleaned out unused signals 2021-02-26 09:17:36 -05:00
kaveh pezeshki
c7863d58cd merged with main to integrate with AHB 2021-02-26 05:37:10 -08:00
David Harris
b16846bddb Clean up bus interface code 2021-02-26 01:03:47 -05:00
David Harris
24f767a404 Retimed peripherals for AHB interface 2021-02-26 00:55:41 -05:00
David Harris
c060e427f0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-02-25 15:49:38 -05:00
David Harris
a16fd95eed Restored to working multiplier after Lab 2 2021-02-25 15:32:43 -05:00
Brett Mathis
ec82453ba1 FPU Assembly tests 2021-02-25 14:32:36 -06:00
Teo Ene
6be5bb1f84 Fixed previous commit 2021-02-25 11:24:44 -06:00
Teo Ene
31c07b2adc Edited imem to account for TIMBASE==0; still hard-coded and needs to be improved, but works with coremark config now. 2021-02-25 11:23:01 -06:00
David Harris
d00d42cf9a Merged bus into main 2021-02-25 00:28:41 -05:00
David Harris
f5e9c91193 All tests passing with bus interface 2021-02-24 07:25:03 -05:00
Katherine Parry
8f5cc19143 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-02-23 20:21:53 +00:00
Katherine Parry
7b103423e1 inital FMA push 2021-02-23 20:19:12 +00:00
Noah Boorstin
ceb7df3561 busybear: instantiate soc instead of hart 2021-02-23 18:59:06 +00:00
David Harris
c52a99ce2d Fixed fetch stall after jump in bus unit 2021-02-23 09:08:57 -05:00
David Harris
817f81c356 Debugging Bus interface 2021-02-22 13:48:30 -05:00
kaveh pezeshki
62d9185212 Merge remote-tracking branch 'origin/tlb_toy' into busybear 2021-02-22 02:23:01 -08:00
Ross Thompson
9b3637bd87 RAS needs to be reset or preloaded. For now I just reset it. 
Fixed bug with the instruction class.
Most tests now pass.  Only Wally-JAL and the compressed instruction tests fail.  Currently the bpred does not support compressed.  This will be in the next version.
 2021-02-19 20:09:07 -06:00
Ross Thompson
00de91cc87 Added FlushF to hazard unit. 
Fixed some typos with the names of signals in the branch predictor.  They were causing signals to be not set.  Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
 2021-02-19 16:36:51 -06:00
Ross Thompson
c6ebe7733b Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary. 
About 149307ns of simulation run.
 2021-02-18 21:32:15 -06:00
Thomas Fleming
21552eaf9d Create simple TLB 
This TLB is just a demonstration and is not currently
instantiated by the IFU or DFU.
 2021-02-18 18:06:09 -05:00
David Harris
acd7ba8b60 Updated creation date of mul 2021-02-18 08:13:08 -05:00