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578 Commits 14 Branches 1 Tag 31 MiB
7e9a0602ea
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226 Commits

Author SHA1 Message Date
Shreya Sanghai
7e9a0602ea fixed bugs in global history to read latest GHRE 
Cherry pick Shreya's commits into main branch.
 2021-04-15 08:55:22 -05:00
bbracker
8f7ddcfdff rv64 interrupt servicing 2021-04-14 10:19:42 -04:00
Thomas Fleming
7d2d6823f1 Fix mmu lint errors 2021-04-13 19:19:58 -04:00
Thomas Fleming
0a9b208729 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-13 17:15:10 -04:00
Katherine Parry
ef011496a7 Various bugs fixed in FMA 2021-04-13 18:27:13 +00:00
Thomas Fleming
09c9c49541 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/pagetablewalker.sv
 2021-04-13 13:42:03 -04:00
Thomas Fleming
6188f10732 Move InstrPageFault to fetch stage 2021-04-13 13:39:22 -04:00
Thomas Fleming
dc8a165806 Add lru algorithm to TLB 2021-04-13 13:37:24 -04:00
Teo Ene
1018a10625 Various code syntax changes to bring HDL to a synthesizable level 2021-04-13 11:27:12 -05:00
Ross Thompson
35f8b4f74f Fixed minor bug in muldiv which corrects the lint error. 2021-04-09 10:56:31 -05:00
Katherine Parry
f4cb92ae71 fixed FPU lint warnings 2021-04-08 18:03:21 +00:00
Katherine Parry
27cb94e7af fixed FPU lint warnings 2021-04-08 17:55:25 +00:00
Domenico Ottolia
65abe13f4f Cause an Illegal Instruction Exception when attempting to write readonly CSRs 2021-04-08 05:12:54 -04:00
Thomas Fleming
fc39535e4e Refactor TLB into multiple files 2021-04-08 03:24:10 -04:00
Thomas Fleming
c54aecde73 Provide attribution link for priority encoder 2021-04-08 03:05:06 -04:00
Thomas Fleming
303c2c4839 Implement support for superpages 2021-04-08 02:44:59 -04:00
bbracker
38017e6aae declare memread signal 2021-04-05 08:13:01 -04:00
bbracker
a4c3afb847 PLIC claim reg side effects now check for memread signal 2021-04-05 08:03:14 -04:00
bbracker
4a5aa5b202 plic subword access compliance 2021-04-04 23:10:33 -04:00
Katherine Parry
e6a7353847 Added missing files in FPU 2021-04-04 18:09:13 +00:00
bbracker
31c6b2d01f Yee hoo first draft of PLIC plus self-checking tests 2021-04-04 06:40:53 -04:00
Thomas Fleming
6b43381c38 Comment out fpu from hart until module exists 2021-04-03 22:34:11 -04:00
Thomas Fleming
dbd5a4320e Merge branch 'mmu' into main 
Conflicts:
	wally-pipelined/src/wally/wallypipelinedhart.sv
 2021-04-03 22:12:52 -04:00
Thomas Fleming
8dfec29f7e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-03 22:09:50 -04:00
Thomas Fleming
1cbdaf1f05 Fix extraneous page fault stall 2021-04-03 21:28:24 -04:00
Katherine Parry
d7b1379ab8 Integrated FPU 2021-04-03 20:52:26 +00:00
Ross Thompson
d21006d048 Partial fix to the integer divide stall issue. 2021-04-02 15:32:15 -05:00
James E. Stine
362f6ea2e6 Minor cleanup 2021-04-02 08:20:44 -05:00
James E. Stine
cff08adc3a Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal. 2021-04-02 06:27:37 -05:00
Thomas Fleming
bfb4b051c6 Merge branch 'main' into mmu 2021-04-01 16:29:39 -04:00
Thomas Fleming
350fe87119 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-01 16:24:06 -04:00
Thomas Fleming
fdb20ee1cf Implement sfence.vma and fix tlb writing 2021-04-01 15:55:05 -04:00
James E. Stine
0495195d68 Fixed some divide -still bug in AHB causing InstStall to deassert and next instruction to get into divide unit. Hope to fix soon. Divide seems to work if given enough time. 2021-04-01 12:30:37 -05:00
Thomas Fleming
77b8e27205 Disable 'always-on' virtual memory 2021-03-30 22:49:47 -04:00
Thomas Fleming
eca2427f94 Merge remote-tracking branch 'origin/main' into main 
Bring icache and MMU code together

Conflicts:
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 22:24:47 -04:00
Thomas Fleming
7126ab7864 Complete basic page table walker 2021-03-30 22:19:27 -04:00
ushakya22
6b9ae41302 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
Brett Mathis
162f2df880 FPU Pipeline completed - can begin integration 2021-03-25 13:29:03 -05:00
Thomas Fleming
e3900bd0fa Finish finite state machines for page table walker 2021-03-25 02:48:40 -04:00
Thomas Fleming
b5003b093a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-25 02:35:21 -04:00
bbracker
a3788eb218 added 1 tick delay to dtim flops 2021-03-25 02:23:30 -04:00
bbracker
02e924e55a instrfaults not respecting stalls bugfix 2021-03-25 00:16:26 -04:00
bbracker
1e3f683a9d upgraded gpio bus interface 2021-03-25 00:15:02 -04:00
bbracker
e98dd420bc future work comment about suspicious-looking verilog in csri.sv 2021-03-25 00:10:44 -04:00
Thomas Fleming
b1d849c822 Add all PMP addr registers 2021-03-24 21:58:33 -04:00
Katherine Parry
18cb1f4873 fixed various bugs in the FMA 2021-03-24 21:51:17 +00:00
Katherine Parry
56dc8de009 fixed various bugs in the FMA 2021-03-24 01:35:32 +00:00
Teo Ene
ef3d2dda48 Added BOOTTIM to InstrAccessFaultF calculation in uncore/imem 2021-03-23 15:21:13 -05:00
Shreya Sanghai
1d6a2989ed PC counts branch instructions 2021-03-23 14:25:51 -04:00
bbracker
5efd5958e7 added delays to uart AHB signals 2021-03-22 15:40:29 -04:00