bbracker
c26526c9f3
change RX side of UART to aslo be LSB-first
2022-02-22 03:34:08 +00:00
Ross Thompson
1ab2e7590b
Added some clearity to lsuvirtmem.sv.
2022-02-21 17:20:58 -06:00
Ross Thompson
8a280f211f
Annotated IFU for mux changes.
2022-02-21 17:20:34 -06:00
Ross Thompson
ace743ae91
Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW.
2022-02-21 16:54:38 -06:00
Ross Thompson
414e73edd9
Cleaned up names in lsuvirtmem.
2022-02-21 16:44:30 -06:00
Ross Thompson
456a54166a
Minor cleanup of lsu.
2022-02-21 12:46:06 -06:00
Ross Thompson
5d9ad011d2
Moved mux into lsuvirtmem.
2022-02-21 09:31:29 -06:00
Ross Thompson
8af055c78e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-21 09:06:09 -06:00
Ross Thompson
a60332b455
Minor changes to LSU.
2022-02-19 14:38:17 -06:00
David Harris
4e194b2576
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-18 23:08:47 +00:00
David Harris
a88302f0d7
Removed problematic warning about reaching default state in HPTW
2022-02-18 23:08:40 +00:00
Ross Thompson
0bd533473c
New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.
2022-02-17 17:19:41 -06:00
Ross Thompson
a7b774e453
Accidentally cleared dirty bit when setting access bit in hptw.
2022-02-17 16:20:20 -06:00
Ross Thompson
7dffcba182
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-17 14:49:37 -06:00
Ross Thompson
d152733a17
Rough implementation passing regression test with hptw atomic writes to memory.
2022-02-17 14:46:11 -06:00
David Harris
3036de316a
Started make allsynth to try many experiments
2022-02-17 17:57:02 +00:00
Ross Thompson
4cfb601dc8
Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB.
2022-02-17 10:04:18 -06:00
Ross Thompson
565ca4e4a3
Broken state. address translation not working after changes to hptw to support atomic updates to PT.
2022-02-16 23:37:36 -06:00
Ross Thompson
beac362364
Moved a few muxes around after sww changes.
2022-02-16 15:43:03 -06:00
Ross Thompson
6a2bcfcd01
cleanup of signal names.
2022-02-16 15:29:08 -06:00
Ross Thompson
84edb8b5d5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-16 15:22:35 -06:00
Ross Thompson
bd7343b791
Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path.
2022-02-16 15:22:19 -06:00
David Harris
131a1a4ded
Cleaned warning on HPTW default state
2022-02-16 17:40:13 +00:00
David Harris
799736632b
Register file comments about reset
2022-02-16 17:21:05 +00:00
Ross Thompson
a64839d999
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-16 09:48:16 -06:00
David Harris
72e83db9fe
removed csrn and all of its outputs because depricated
2022-02-15 19:59:29 +00:00
David Harris
d3034c4f01
Mostly removed N_SUPPORTED
2022-02-15 19:50:44 +00:00
David Harris
f734afb866
Just needed to recompile - all good. Now removed uretM because N-mode is depricated
2022-02-15 19:48:49 +00:00
David Harris
1326ade1a0
Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change.
2022-02-15 19:20:41 +00:00
Ross Thompson
6076f90bbc
Cache mods to be consistant with diagrams.
2022-02-14 12:40:51 -06:00
David Harris
1d5c8a7b98
t push
...
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-14 01:22:22 +00:00
Ross Thompson
1bb4d46ac1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-13 18:21:15 -06:00
Ross Thompson
e852cb8a31
Eliminated more ports in cacheway.
2022-02-13 15:53:46 -06:00
Ross Thompson
1d7949513d
More cache cleanup.
2022-02-13 15:47:27 -06:00
Ross Thompson
7ffbc6b2ab
Changed names of signals in cache.
2022-02-13 15:06:18 -06:00
Ross Thompson
a5ad4331ec
More cache cleanup.
2022-02-13 12:38:39 -06:00
David Harris
b360e7b941
Synthesis cleanup
2022-02-12 06:25:12 +00:00
David Harris
a34cbdb7d0
Synthesis script cleanup, eliminated privileged instructiosn from controller when ZICSR_SUPPORTED = 0
2022-02-12 05:50:34 +00:00
Ross Thompson
dd944265aa
Formating improvements to cache.
2022-02-11 23:10:58 -06:00
Ross Thompson
bf173b035c
More cache simplifications.
2022-02-11 22:54:05 -06:00
Ross Thompson
16abe90a0d
Reduced seladr to 1 bit as second bit is same as selflush.
2022-02-11 22:41:36 -06:00
Ross Thompson
b11e9eca7b
Reduced complexity of the address selection during flush.
2022-02-11 22:27:27 -06:00
Ross Thompson
1255e82154
Removed redundant signals from cache.
2022-02-11 22:23:47 -06:00
Ross Thompson
52894a7a4f
Cache fsm simplifications.
2022-02-11 15:16:45 -06:00
Ross Thompson
e2e0a4f595
Removed STATE_CPU_BUSY_FINISH_AMO from cache. This is redundant with STATE_CPU_BUSY.
2022-02-11 15:09:00 -06:00
Ross Thompson
0f2ac0cb24
Simplified cache fsm.
2022-02-11 14:54:57 -06:00
Ross Thompson
1c83914662
Fixed bug.
...
It was possible for DTLBMissM to prevent a dcache flush.
2022-02-11 14:00:01 -06:00
Ross Thompson
febd019854
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-11 10:47:21 -06:00
Ross Thompson
6d12010d02
Fixed subtle and infrequenct bug.
...
Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
2022-02-11 10:46:06 -06:00
David Harris
de5e80696d
Cleaned up synthesis warnings
2022-02-11 01:15:16 +00:00
Ross Thompson
689c32215f
Fixed bugs in ifu spills and missing reset on bus data register.
2022-02-10 18:11:57 -06:00
Ross Thompson
5fd22caed4
Replacement policy cleanup.
2022-02-10 11:42:40 -06:00
Ross Thompson
f716cce832
Replacement policy cleanup.
2022-02-10 11:40:10 -06:00
Ross Thompson
104a9acf81
Cleanup.
2022-02-10 11:27:15 -06:00
Ross Thompson
fdb4f909fc
Cleanup + critical path optimizations.
2022-02-10 11:11:16 -06:00
Ross Thompson
88c7a94aa9
Cache name clarifications.
2022-02-10 10:50:17 -06:00
Ross Thompson
32eee5a06a
More cache cleanup.
2022-02-10 10:43:37 -06:00
Ross Thompson
91f2b5adf5
structural muxes.
2022-02-09 19:36:21 -06:00
Ross Thompson
7ff715f44f
More cache cleanup.
2022-02-09 19:29:15 -06:00
Ross Thompson
754bd41fde
Cleaned up comments.
2022-02-09 19:21:35 -06:00
Ross Thompson
36ab78ef3b
Removed all possilbe paths to PreSelAdr from TrapM.
2022-02-09 19:20:10 -06:00
Ross Thompson
7810a09782
Annotated the final changes required to move sram address off the critial path.
2022-02-08 18:17:31 -06:00
Ross Thompson
30d6514661
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-08 17:52:15 -06:00
Ross Thompson
4a7ebb3757
Cache cleanup write enables.
2022-02-08 17:52:09 -06:00
Ross Thompson
bdb3794d5e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-08 15:43:18 -06:00
Ross Thompson
c2907ec0f4
Cleanup IFU.
2022-02-08 14:54:53 -06:00
Ross Thompson
038897f448
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-08 14:47:15 -06:00
Ross Thompson
4273775a2b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-08 14:22:19 -06:00
Ross Thompson
e02bc8db67
rv32e works for now. Still need to optimize.
2022-02-08 14:21:55 -06:00
Ross Thompson
f211fe635a
Moved some muxes back into the bp.
2022-02-08 14:17:44 -06:00
David Harris
1479762ae9
RAM simplification
2022-02-08 20:15:23 +00:00
Ross Thompson
aa12d90272
Temporary commit which gets the no branch predictor implementation working.
2022-02-08 14:13:55 -06:00
Ross Thompson
8a2ee22395
Finished merge.
2022-02-08 11:36:24 -06:00
Ross Thompson
e2191e3637
Preparing to make a major change to the cache's write enables.
2022-02-08 09:47:01 -06:00
David Harris
c61cd55c5c
Merged TIM and regular testbenches. RV32e now working and back in regression.
2022-02-08 12:18:13 +00:00
Ross Thompson
5c9e23527d
cachefsm cleanup.
2022-02-07 22:09:56 -06:00
Ross Thompson
da2dca9816
Removed VDWriteEnable.
2022-02-07 21:59:18 -06:00
Ross Thompson
161f907cae
more partial cleanup of fsm and write enables.
2022-02-07 17:41:56 -06:00
Ross Thompson
359a23237d
Progress towards simplifying the cache's write enables.
2022-02-07 17:23:09 -06:00
Ross Thompson
188fe28691
more cleanup.
2022-02-07 13:29:19 -06:00
Ross Thompson
9510a33c15
More cachefsm cleanup.
2022-02-07 13:19:37 -06:00
Ross Thompson
708e0cf183
More cachefsm cleanup.
2022-02-07 12:30:27 -06:00
Ross Thompson
5539a5fa6f
More cachefsm cleanup.
2022-02-07 11:16:20 -06:00
Ross Thompson
6668956351
More cachefsm cleanup.
2022-02-07 11:12:28 -06:00
Ross Thompson
5536e3ca90
More cachefsm cleanup.
2022-02-07 10:54:22 -06:00
Ross Thompson
529d8b629a
Cache cleanup.
2022-02-07 10:43:58 -06:00
Ross Thompson
41a79556e0
More cachfsm cleanup.
2022-02-07 10:33:50 -06:00
David Harris
99f3d7a7f6
Reverted cache change
2022-02-07 14:47:20 +00:00
David Harris
45dc9c1ae6
Cache syntax cleanup
2022-02-07 14:43:24 +00:00
Ross Thompson
0b66106925
More cachefsm cleanup.
2022-02-06 21:50:44 -06:00
Ross Thompson
dd6baa9ed4
started cachefsm cleanup.
2022-02-06 21:39:38 -06:00
David Harris
9b55848ffc
Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration
2022-02-06 01:22:40 +00:00
Ross Thompson
d21be9d998
Added config to allow using the save/restore or replay implementation to handle sram clocked read delay.
2022-02-04 23:49:07 -06:00
Ross Thompson
ea84211ff9
Removed unused ports from caches and buses.
2022-02-04 22:52:51 -06:00
Ross Thompson
011ad09341
Cleanup.
2022-02-04 22:40:51 -06:00
Ross Thompson
4074f695e0
Moved the hwdata mux back into the busdp.
2022-02-04 22:39:13 -06:00
Ross Thompson
40eb055861
Merged together the two sub cache line read muxes.
...
One mux was used for loads and the other for eviction.
2022-02-04 22:30:04 -06:00
David Harris
72bc64ef28
Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.
2022-02-05 04:16:18 +00:00
Ross Thompson
290430cda8
Moved the sub cache line read logic to lsu/ifu.
2022-02-04 20:42:53 -06:00
Ross Thompson
725852362e
Got separate module for the sub cache line read.
2022-02-04 20:23:09 -06:00
