Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity
5,277 Commits 14 Branches 1 Tag 31 MiB
2edcb9d842
Commit Graph

2184 Commits

Author SHA1 Message Date
Ross Thompson
3e1a54e80a Removed SDC from repo due to copy right issue. 
Modified fpga build flow to reference it outside the repo.
 2023-01-20 14:57:06 -06:00
Ross Thompson
2e9b5f9ae4 Formatting. 2023-01-20 13:13:05 -06:00
Ross Thompson
bcadbd7104 Formatting. 2023-01-20 13:09:42 -06:00
Ross Thompson
ecceea177a Formatting. 2023-01-20 13:05:10 -06:00
Ross Thompson
3d202ed2fd Reformatting cachefsm. 2023-01-20 12:49:55 -06:00
Ross Thompson
d3df8e062e Formatting. 2023-01-20 12:41:57 -06:00
Ross Thompson
1ecf4e4cc9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-20 12:37:12 -06:00
Ross Thompson
74ab386735 More cleanup and formatting. 2023-01-20 12:34:40 -06:00
David Harris
26cb45e240 renamed comparator module 2023-01-20 10:13:47 -08:00
Ross Thompson
340e1797ea More cleanup and formatting. 2023-01-20 12:09:21 -06:00
Ross Thompson
c5169a3e39 Formatting. 2023-01-20 11:51:10 -06:00
Ross Thompson
5b5a615e4a Integrated the missing zifence tests into the regression test. 2023-01-20 10:34:49 -06:00
Ross Thompson
29f45d6203 Imperas found a bug with the Fence.I instruction. 
If a fence.i directly followed a store miss, the d$ would release Stall during the cache line write.
Then transition to ReadHold.  This cause the d$ flush to go high while in ReadHold.  The solution is
to ensure the cache continues to assert Stall while in WriteLine state.

There was a second issue also.  The D$ flush asserted FlushD which flushed the I$ invalidate.
Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache.
 2023-01-20 10:17:21 -06:00
Ross Thompson
2cca457f14 Imperas found a bug with the Fence.I instruction. 
If a fence.i directly followed a store miss, the d$ would release Stall during the cache line write.
Then transition to ReadHold.  This cause the d$ flush to go high while in ReadHold.  The solution is
to ensure the cache continues to assert Stall while in WriteLine state.

There was a second issue also.  The D$ flush asserted FlushD which flushed the I$ invalidate.
Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache.
 2023-01-20 09:41:18 -06:00
Ross Thompson
da4eec7e0e Improved comment. 2023-01-19 17:41:57 -06:00
Ross Thompson
117ff8163b ram uses always rather than always_ff due to modelsim issue. 2023-01-19 17:41:15 -06:00
Ross Thompson
23ab178192 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-19 17:28:53 -06:00
Ross Thompson
928e06d4fa Added comment about needed changes in BTB. 2023-01-19 17:28:00 -06:00
David Harris
569a016efa Removed study versions from comparator 2023-01-19 15:13:35 -08:00
David Harris
0488723db9 Moved unused study files to studies directory 2023-01-19 15:13:11 -08:00
David Harris
9df5fdbd89 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-19 14:47:54 -08:00
David Harris
25b607566c RAM declaration cleanup: 2023-01-19 14:47:51 -08:00
Ross Thompson
b027921902 Formatting. 2023-01-19 15:06:37 -06:00
Ross Thompson
ea96c2375f Formatting. 2023-01-19 14:18:46 -06:00
Ross Thompson
e380fd71ff Formatting and name changes. 2023-01-19 14:16:29 -06:00
eroom1966
d9d5b99218 update 2023-01-19 13:29:46 +00:00
Ross Thompson
47fdff6488 Formatting. 2023-01-18 19:26:20 -06:00
Ross Thompson
49daa736b1 Formatting spillsupport. 2023-01-18 19:25:54 -06:00
Ross Thompson
cd2f7c6208 Formatting. 2023-01-18 19:11:30 -06:00
Ross Thompson
7289fa8d44 Reduced complexity of spill logic by ensuring the irom outputs offset instrutions on a spill. 2023-01-18 19:10:34 -06:00
Ross Thompson
026d09b79b More IROM cleanup. 2023-01-18 18:47:02 -06:00
Ross Thompson
19e4d0f7cd Cleanup dtim and irom. 2023-01-18 18:44:30 -06:00
Ross Thompson
997dda11a8 Added comments to decompress.sv. May want to consider additional documentation. 2023-01-18 18:26:51 -06:00
Ross Thompson
fb234d506d Formatted subword* and bytemask. 2023-01-18 18:20:22 -06:00
Ross Thompson
469efa61af Formatting. 2023-01-18 18:17:48 -06:00
Ross Thompson
cbf46f417a Formatting. 2023-01-18 18:16:56 -06:00
Ross Thompson
22eee73a45 Formatting. 2023-01-18 18:16:20 -06:00
Ross Thompson
2048edb7a0 Renamed signals in amoalu. 2023-01-18 18:13:18 -06:00
Ross Thompson
40c0e67930 Formatting. 2023-01-18 18:05:11 -06:00
Ross Thompson
2622f5dfb8 Formatting. 2023-01-18 17:56:47 -06:00
Ross Thompson
a6b14eb9ee Formatting. 2023-01-18 17:49:19 -06:00
Ross Thompson
0b244e289c Formating. 2023-01-18 17:30:08 -06:00
Ross Thompson
affca27ec4 Formatting 2023-01-18 17:14:37 -06:00
Ross Thompson
58a07399a2 Formatting 2023-01-18 17:03:45 -06:00
Ross Thompson
fc5424fa62 Formatting 2023-01-18 16:58:03 -06:00
Ross Thompson
607c64e0ee Formating. 2023-01-18 16:52:46 -06:00
Ross Thompson
c34acab1d7 Formating. 2023-01-18 16:47:40 -06:00
David Harris
915987c524 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-18 13:07:03 -08:00
David Harris
331ef80d0f removed fma directory, improved plic comments 2023-01-18 13:06:54 -08:00
eroom1966
7c0cad148d Partial fix for misaligned LD/ST 2023-01-18 17:11:39 +00:00
eroom1966
2e4e5f9c61 changes made with Ross 2023-01-18 16:46:48 +00:00
sarah-harris
789fc0e493 Minor fixes in datapath.sv and ieu.sv (comments, putting signals in correct grouping) 2023-01-18 07:26:08 -08:00
eroom1966
a5a5b7a408 add im flags for compressed disass 2023-01-18 13:37:28 +00:00
eroom1966
df4419dea2 remove volatile for FFLAGS and FCSR 2023-01-18 13:33:57 +00:00
eroom1966
c18942bd0b refer to correct path 2023-01-18 13:26:07 +00:00
Ross Thompson
a929e53576 More comments added to abhfsm. 2023-01-17 22:58:06 -06:00
Ross Thompson
4bfabc4136 formating ahbinterface. 2023-01-17 22:54:42 -06:00
Ross Thompson
4b47598138 Moved amoalu to lsu. 2023-01-17 22:45:46 -06:00
Ross Thompson
8f4f17a4c8 Added commenets and formating to abhcachefsm and abhcacheinterface. 2023-01-17 22:22:23 -06:00
Ross Thompson
f146a01344 Cleaned up ahbcacheinterface. 2023-01-17 22:13:56 -06:00
Ross Thompson
d6c80d937c Formatting progress. 2023-01-17 22:10:31 -06:00
Ross Thompson
c75a164f46 Added comments to dtim and ahbcacheinterface. 2023-01-17 21:56:55 -06:00
Ross Thompson
97661a023a Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-17 21:54:55 -06:00
Ross Thompson
b30c13a188 Fixed the rvvi CSR write enable not synchronized with a valid instruction in the Writeback stage. 2023-01-17 18:24:46 -06:00
Ross Thompson
aa942feedc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2023-01-17 15:44:44 -06:00
David Harris
c73bea83cd Clean up warnings from Questa 2023-01-17 13:43:39 -08:00
Ross Thompson
caff6e788c Somehow the imperas files spilled into the main branch. 2023-01-17 15:39:34 -06:00
Ross Thompson
c6e366b86e Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-17 14:50:45 -06:00
David Harris
555fee94fa IEU comment cleanup 2023-01-17 10:51:44 -08:00
David Harris
77766a6dac Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-17 06:47:06 -08:00
David Harris
c8d77d785c IEU signal comment cleanup 2023-01-17 06:47:02 -08:00
sarah-harris
4e9a7a6403 Changing signal name to ImmExtD/E to match figures 
Changing signal name:
ExtImmD/E -> ImmExtD/E

to match figures.
 2023-01-17 06:33:58 -08:00
David Harris
15866cb11d pipelined/src/ieu/ieu.sv 2023-01-17 06:08:26 -08:00
sarah-harris
cb153d74d9 IEU cleanup 
IEU cleanup
 2023-01-17 06:02:26 -08:00
eroom1966
8caa93ce4d refactor all rvvi into single initial block 2023-01-17 13:01:01 +00:00
eroom1966
f4e7e54abe Code refactor and addition of rvvi interface 2023-01-17 12:47:38 +00:00
Ross Thompson
c65becbae5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-16 14:03:05 -06:00
Ross Thompson
7c4eaa1ca6 Found a potential issue with mstatush when XLEN = 64. 2023-01-16 13:57:28 -06:00
Ross Thompson
fabe13bdce Fixed issue with rvvi tracer so it reports call csr changes, not just instrutions which write the CSRs. 2023-01-16 13:35:06 -06:00
David Harris
f93b7cfda7 Removed Imperas tests from regression 2023-01-16 07:01:07 -08:00
David Harris
12e12e464a Makefile and setup cleanup 2023-01-15 20:27:12 -08:00
David Harris
7f68a55b8c Clean up tabs 2023-01-15 18:23:09 -08:00
Ross Thompson
8a0e38fd92 Fixed bug with gshare repair from branch class miss prediction. 2023-01-15 14:39:48 -06:00
David Harris
56dac4be7d cache cleanup 2023-01-14 19:43:29 -08:00
David Harris
08fca1c517 ebu cleanup 2023-01-14 19:29:45 -08:00
David Harris
a6d8511a2e ebu cleanup 2023-01-14 19:19:34 -08:00
David Harris
91afe5522b generic cleanup 2023-01-14 19:02:38 -08:00
David Harris
9c79078be1 generic cleanup 2023-01-14 18:56:46 -08:00
David Harris
93b0286934 mmu cleanup 2023-01-14 18:27:53 -08:00
David Harris
9d51abc2e1 mmu cleanup 2023-01-14 18:20:47 -08:00
David Harris
ee1b4fe221 mmu cleanup 2023-01-14 18:14:38 -08:00
David Harris
7c5548a39c mmu cleanup 2023-01-14 17:49:10 -08:00
David Harris
939bf3f148 mmu cleanup 2023-01-14 17:35:21 -08:00
David Harris
697a8d8f50 uncore cleanup 2023-01-14 17:21:07 -08:00
David Harris
a4c753635e uncore cleanup 2023-01-14 17:09:11 -08:00
David Harris
a2b455d7b5 uncore cleanup 2023-01-14 17:07:36 -08:00
David Harris
f16267ddbc uncore cleanup 2023-01-14 17:00:58 -08:00
David Harris
1ec42b9d50 sdc cleanup 2023-01-14 16:49:44 -08:00
David Harris
3ad4ae352c uncore cleanup 2023-01-14 06:15:35 -08:00
David Harris
0c91505f41 Wallypipeliendcore/soc cleanup 2023-01-14 05:57:50 -08:00
David Harris
10f76dd7e6 csr & wally cleanup 2023-01-13 22:25:19 -08:00
David Harris
efe7e88258 csr cleanup 2023-01-13 22:12:06 -08:00
David Harris
90e7aa2d50 csr cleanup 2023-01-13 21:29:03 -08:00
David Harris
9526479782 csr cleanup 2023-01-13 21:25:55 -08:00
David Harris
c9c174de49 csr cleanup 2023-01-13 21:09:29 -08:00
David Harris
be236d9438 csr cleanup 2023-01-13 21:00:06 -08:00
David Harris
50415a0a12 csr cleanup 2023-01-13 20:55:21 -08:00
David Harris
25d8566694 csr comments 2023-01-13 20:49:34 -08:00
David Harris
543d9d379b trap comments 2023-01-13 19:50:44 -08:00
David Harris
b613722617 trap comments 2023-01-13 19:44:38 -08:00
David Harris
74d3e0aa40 privileged comments 2023-01-13 17:57:38 -08:00
Ross Thompson
4c78bcade8 Possible improvement to gshare. 2023-01-13 18:50:01 -06:00
Ross Thompson
76a9e7d963 Merge branch 'rastemp' 2023-01-13 18:09:50 -06:00
Ross Thompson
886e4e2935 Partial fix to RAS prediction accurracy. 2023-01-13 18:05:47 -06:00
Ross Thompson
4aa2b5737f Signal renames for ras. 2023-01-13 15:56:10 -06:00
Ross Thompson
0e215ac3c6 Removed 1 bit from instruction classification. 2023-01-13 15:19:53 -06:00
Ross Thompson
de7f3b14fc More branch predictor cleanup. 
Found small bug. The decode stage was using the predicted instruction class rather than the decoded instruction class.
 2023-01-13 12:57:18 -06:00
Ross Thompson
cf608ee45f Possible optimization of gshare. 
I don't believe the Writeback stage ghr is needed.
 2023-01-13 12:39:29 -06:00
Ross Thompson
ea7c447218 Possible minor enhancement to gshare. 2023-01-13 12:32:39 -06:00
Ross Thompson
55169fa9b0 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2023-01-13 10:26:07 -06:00
Ross Thompson
395b7a5b32 Nearly complete RVVI tracer. 
Missing PMP registers and performance counters other than MCYCLE and MINSTRET.
 2023-01-12 18:43:39 -06:00
Ross Thompson
ef4c684336 Added supervisor mode registers to tracer. 2023-01-12 17:04:41 -06:00
Ross Thompson
9917be817c Added M CSRs to the CSRArray. 2023-01-12 16:51:51 -06:00
Ross Thompson
a68773eba1 added machine csr to logger. 2023-01-12 16:35:19 -06:00
Ross Thompson
2e622c9860 Added support to print the gprs. 2023-01-12 16:09:30 -06:00
Ross Thompson
4733b787f8 rvvi trace is coming alone nicely. 2023-01-12 14:46:31 -06:00
Ross Thompson
3cc37e3f12 Completely stripped down imperas simulation. 
run with
vsim -c -do "do wally-pipelined-imperas.do rv64gc"
 2023-01-12 12:48:38 -06:00
Ross Thompson
2f2f3d6da5 Stripped out all signature checking. 
Removed multiple tests loop.
Only runs 1 test now.
 2023-01-12 12:45:44 -06:00
Ross Thompson
5ad0bacf5b Created separate imperas testbench. 
Resolved logger issue with the duplicated instructions after commit.
 2023-01-12 12:07:07 -06:00
Ross Thompson
94f24d3f58 Added instruction logger. 2023-01-12 10:09:34 -06:00
David Harris
fdcb1f08ce Privileged unit formatting 2023-01-12 07:41:30 -08:00
David Harris
e58879f2d0 restructured code for lint error related to CORRSHIFTSZ 2023-01-12 07:34:37 -08:00
David Harris
93233fbb45 Restructured negateintres to avoid lint error, but one still shows on shiftcorrection 2023-01-12 07:28:52 -08:00
David Harris
1ad6ac1393 MDU comment cleanup 2023-01-12 07:15:14 -08:00
David Harris
768c1bc703 Header comments 2023-01-12 04:35:44 -08:00
Ross Thompson
b96a53df0a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2023-01-11 23:02:14 -06:00
Katherine Parry
77a982c977 cleaned up all FPU files except for division 2023-01-11 22:02:30 -06:00
David Harris
67d474995e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-11 19:48:37 -08:00
David Harris
bfd47ff7f5 Removed unused wallypipelinedsocwrapper 2023-01-11 19:48:34 -08:00
Ross Thompson
e0867b1840 Completed review of LSU. 2023-01-11 19:06:03 -06:00
Ross Thompson
aba1df9abf Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-11 18:52:49 -06:00
Ross Thompson
318ceba34d Improved LSU formating. 2023-01-11 18:52:46 -06:00
sarah-harris
796a189451 privilege unit -> privileged unit in ifu.sv 
privilege unit -> privileged unit in ifu.sv
 2023-01-11 16:33:08 -08:00
Ross Thompson
ad22a9ea02 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-11 17:26:11 -06:00
sarah-harris
203cc164d9 Added Sarah.Harris@unlv.edu to alu.sv 
Added Sarah.Harris@unlv.edu to alu.sv
 2023-01-11 15:20:41 -08:00
Ross Thompson
b60e9730a7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-11 17:15:49 -06:00
David Harris
8c6ddcc15b changed name to CORE-V-WALLY 2023-01-11 15:15:08 -08:00
Ross Thompson
bccef3b39c Updated header for LSU. 2023-01-11 17:15:07 -06:00
David Harris
9a057ef5cd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-11 15:13:58 -08:00
Ross Thompson
a8931e0211 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-11 17:09:23 -06:00
Katherine Parry
4556839960 fixed typo bug in fpu 2023-01-11 17:07:02 -06:00
Ross Thompson
6999b4562e Updated branch predictor. 2023-01-11 17:00:45 -06:00
David Harris
3ea4dd4898 Changed Wally to CORE-V Wally 2023-01-11 14:03:44 -08:00
David Harris
99ff78b902 FPU cleanup 2023-01-11 12:27:00 -08:00
David Harris
4ff2627a50 fpu cleanup 2023-01-11 12:18:06 -08:00
David Harris
d1bfdddd8c Rename FP and FPU to F in signal names 2023-01-11 11:46:36 -08:00
David Harris
15026f61f7 FPU comments 2023-01-11 11:31:28 -08:00
David Harris
654abcde61 Replaced MDUE with IntDivE in FDIVSQRT 2023-01-11 11:06:37 -08:00
Ross Thompson
1df9c5f13e Optimized gshare. 2023-01-10 18:12:48 -06:00
David Harris
f6987fab8c Switched to XZeroE from NumerZeroE in square root preprocessor 2023-01-10 12:37:49 -08:00
David Harris
739c2c8322 Changed MIT license to Solderpad License 2023-01-10 11:35:20 -08:00
David Harris
446b5fa83f Division constant cleanup 2023-01-10 11:14:59 -08:00
David Harris
4a34007b49 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-09 13:04:37 -08:00
David Harris
b2ec52c94d Changed DIVN from NF+3 to NF+2, cleanup 2023-01-09 13:04:34 -08:00
Ross Thompson
f330d877ac Added folded gshare predictor with k=16 and depth=10. 2023-01-09 14:41:03 -06:00
David Harris
48f31d4b24 Divider constant cleanup, made CORRSHIFTSZ consistent 2023-01-09 12:34:19 -08:00
Ross Thompson
302a2e0116 Added better branch predictor to fpga config. 2023-01-09 13:46:30 -06:00
Ross Thompson
ca55bd8444 Fixed branch predictor. 2023-01-09 13:45:49 -06:00
Ross Thompson
6a616617d1 Restored to default configuration. 2023-01-09 00:21:45 -06:00
Ross Thompson
816006ac1b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2023-01-09 00:18:11 -06:00
Ross Thompson
6326e6984c Might have actually solved the gshare bug. 2023-01-09 00:11:25 -06:00
Ross Thompson
6cbce9672d Possibly working speculative global history. 2023-01-08 23:46:53 -06:00
Ross Thompson
0eda4b1ab3 core part of global history works now. forwarding is still broken. 2023-01-08 23:35:02 -06:00
David Harris
d7e420e350 Cache code cleanup 2023-01-07 15:49:18 -08:00
David Harris
dc12291ee3 Cache code cleanup 2023-01-07 15:46:23 -08:00
David Harris
057183bcc9 Cache code cleanup 2023-01-07 15:44:44 -08:00
David Harris
0a25f18a07 Cache code cleanup 2023-01-07 15:42:08 -08:00
David Harris
0ad707f1a5 Cache code cleanup 2023-01-07 15:39:13 -08:00
Ross Thompson
bf08c57ab0 Added branch outcome logger to testbench 2023-01-07 13:16:57 -06:00
Ross Thompson
475becb414 Removed unused rv64BP config. 2023-01-07 12:17:40 -06:00
David Harris
f541a277a8 Remove unused CACHE_ENABLED parameter 2023-01-07 09:57:24 -08:00
David Harris
33c910f952 Remove unused signals 2023-01-07 06:26:29 -08:00
David Harris
dc526c92bd Removed unused signals 2023-01-07 06:06:54 -08:00
David Harris
01525399cc Removed unused signals; added check for atomic in pmachecker 2023-01-07 05:59:56 -08:00
David Harris
21b9f50851 Remove conditional from inside decompress module 2023-01-07 05:51:47 -08:00
David Harris
8506f120e1 Remove unused signals 2023-01-07 05:46:22 -08:00
David Harris
44352ced64 Branch logic simplification and remove unused signals 2023-01-07 05:42:34 -08:00
David Harris
d8f0425467 vclean working; started removing unused signals 2023-01-07 05:34:58 -08:00
David Harris
f4cb652a00 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-07 04:49:40 -08:00
David Harris
2188ff879b code cleanup 2023-01-07 04:49:25 -08:00
Ross Thompson
f119b492bb Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-06 15:18:13 -06:00
Ross Thompson
7223d1e05c Added python script to post process performance counter metrics. 2023-01-06 15:15:54 -06:00
Katherine Parry
1bcb1725f5 renamed alot of signals in fpu 2023-01-06 10:35:23 -06:00
David Harris
c260354817 Removed unused UARCH configuration entries 2023-01-06 05:11:14 -08:00
Ross Thompson
01d4e942d0 Added more missing files. 2023-01-06 00:12:08 -06:00
Ross Thompson
8a5916ce66 Addd missing file. 2023-01-06 00:09:18 -06:00
Ross Thompson
09bb733088 Added code to print out performance counters at end of each test. 2023-01-05 18:00:11 -06:00
Ross Thompson
78e441fb38 More branch predictor cleanup. 2023-01-05 17:19:27 -06:00
Ross Thompson
65dd86b726 Keep around the old gshare. 2023-01-05 15:55:46 -06:00
Ross Thompson
2224679694 Added speculative gshare. 2023-01-05 14:18:00 -06:00