David Harris
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dda035891a
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PIPELINE test running
|
2021-11-01 12:44:35 -07:00 |
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David Harris
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60573b92b2
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Adding custom Wally test infrastructure
|
2021-11-01 08:48:46 -07:00 |
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bbracker
|
fe2cda493c
|
fix buildroot graphical sim
|
2021-10-31 18:33:43 -07:00 |
|
David Harris
|
360930fe8b
|
Fixed exe2memfile parsing of weird line in arch64d test
|
2021-10-30 07:26:18 -07:00 |
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David Harris
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bd1a4769ab
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-10-29 22:32:08 -07:00 |
|
David Harris
|
247f247ad3
|
tesgen cleanup, added riscv-arch-test D tests
|
2021-10-29 22:31:48 -07:00 |
|
David Harris
|
14b9b8126e
|
rearranging testgen
|
2021-10-29 22:28:37 -07:00 |
|
Ross Thompson
|
9c875d38a9
|
Fixed the 4 way set associative pseudo LRU replacement policy.
|
2021-10-29 12:46:02 -05:00 |
|
Ross Thompson
|
41dbb59e24
|
Possible fix for the incorrect behavior of the pseudo LRU replacement policy for 4 ways set associative caches.
|
2021-10-29 11:03:37 -05:00 |
|
Ross Thompson
|
35fcadbe7f
|
Applied batch from fpga branch which fixes the dcache fence bug. The should cause the dcache to flush all dirty cache lines to main memory. The bug caused the dirty reset to clear each way for a particular line.
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2021-10-28 11:07:18 -05:00 |
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bbracker
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7158bf1d4f
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-10-27 14:40:31 -07:00 |
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bbracker
|
ab711c498d
|
checkpoint generator off-by-one error fix
|
2021-10-27 14:10:29 -07:00 |
|
Noah Limpert
|
27251a9935
|
Have replaced .* with signal names in ifu
|
2021-10-27 13:45:37 -07:00 |
|
koooo142857
|
33f5de0f5c
|
aligned all files in ifu folder
|
2021-10-27 12:43:55 -07:00 |
|
David Harris
|
7df4b0c8e7
|
commented out some failing FPU tests
|
2021-10-27 11:27:34 -07:00 |
|
David Harris
|
582c2bf37b
|
Fixed FResultSelM to select proper flags
|
2021-10-27 11:02:42 -07:00 |
|
David Harris
|
589bee5875
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-10-27 10:37:46 -07:00 |
|
David Harris
|
5783e47e1a
|
Changes for floating point sims
|
2021-10-27 10:37:35 -07:00 |
|
Ross Thompson
|
7627e177df
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-10-27 09:59:55 -05:00 |
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Ross Thompson
|
c4170ece27
|
Replaced async reset flip flops with sync reset flip flops in cache and bpread.
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2021-10-27 09:57:11 -05:00 |
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bbracker
|
c457fc6e27
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-10-26 12:43:48 -07:00 |
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bbracker
|
1591a40f68
|
bugfix argument passing to GDB script; remove outdated GDB script
|
2021-10-26 12:43:42 -07:00 |
|
David Harris
|
b7b6d6f23f
|
removed unused signal from wave.do
|
2021-10-26 09:02:22 -07:00 |
|
David Harris
|
90cf37b881
|
commented out nonworking tests
|
2021-10-26 08:56:49 -07:00 |
|
David Harris
|
67adc1d7d5
|
removed referenc outputs
|
2021-10-26 08:51:49 -07:00 |
|
David Harris
|
426a43f77b
|
Forgot to save cacheway merge
|
2021-10-26 08:38:13 -07:00 |
|
David Harris
|
c0145c0a35
|
merging changes
|
2021-10-26 08:34:36 -07:00 |
|
David Harris
|
8287a1ef3e
|
Synchronous reset in non-flop blocks
|
2021-10-26 08:30:35 -07:00 |
|
Ross Thompson
|
c43b19120f
|
Fixed another critical path in the caches.
|
2021-10-25 22:05:11 -05:00 |
|
Ross Thompson
|
1228dbbebc
|
Fixed the timing issue in the cache replacement polcy.
|
2021-10-25 18:00:23 -05:00 |
|
Ross Thompson
|
576383c74b
|
Fixed bug with the changes to sram1rw.
|
2021-10-25 16:11:41 -05:00 |
|
Ross Thompson
|
f0beb4357a
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-10-25 15:36:21 -05:00 |
|
Ross Thompson
|
5fd3f7f2c7
|
Possible fix for critical path timing in caches.
|
2021-10-25 15:33:33 -05:00 |
|
bbracker
|
66e53929ce
|
adapt testbench linux to use reset_ext
|
2021-10-25 13:26:44 -07:00 |
|
bbracker
|
787b54dffc
|
copy / link to checkpoint 8500000 dir
|
2021-10-25 13:24:02 -07:00 |
|
bbracker
|
39efadf2cf
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-10-25 12:25:37 -07:00 |
|
bbracker
|
8c4e6baf48
|
change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros
|
2021-10-25 12:25:32 -07:00 |
|
David Harris
|
fbee4963da
|
Converted flops to synchronous reset now that reset signal is synchronized
|
2021-10-25 11:49:20 -07:00 |
|
David Harris
|
2bf51362e2
|
Added synchronizer to reset
|
2021-10-25 10:05:41 -07:00 |
|
bbracker
|
9b98a499d7
|
some linux testbench cleanup
|
2021-10-25 10:04:30 -07:00 |
|
Ross Thompson
|
76bba541a7
|
Modified the cache's sram model so if it used to synthesize flip flops it terminates the read critical path at the address's input rather than the output read data.
|
2021-10-24 21:21:49 -05:00 |
|
bbracker
|
9fdfc750eb
|
checkpoint initialization bugfix
|
2021-10-24 18:39:51 -07:00 |
|
bbracker
|
13763b002a
|
switch linux graphical sim over to Ross's waves
|
2021-10-24 18:39:23 -07:00 |
|
bbracker
|
fef09e9a5b
|
remove unused scripts
|
2021-10-24 15:19:03 -07:00 |
|
bbracker
|
09959617c6
|
update debugger script to new style
|
2021-10-24 15:18:44 -07:00 |
|
bbracker
|
cc484569cd
|
fix typo
|
2021-10-24 15:05:00 -07:00 |
|
bbracker
|
046a78a8fc
|
manually resolved git merge conflicts in testbench linux after checkpointing
|
2021-10-24 15:02:19 -07:00 |
|
bbracker
|
3531a934c9
|
checkpoint generator bugfix
|
2021-10-24 14:46:56 -07:00 |
|
Ross Thompson
|
8a51fe76c1
|
Partial cleanup of unused signals in caches and bpred.
|
2021-10-24 15:04:20 -05:00 |
|
bbracker
|
c0a7b12f94
|
or actually needed to reduce expectations of buildroot
|
2021-10-24 06:59:34 -07:00 |
|
bbracker
|
d3969bb1ba
|
increase regression's expectations of buildroot
|
2021-10-24 06:50:22 -07:00 |
|
bbracker
|
36b39358c6
|
add checkpointing to linux testbench
|
2021-10-24 06:47:35 -07:00 |
|
bbracker
|
d445095f1b
|
revamp linux testvector generation for refactoring checkpoint generation
|
2021-10-24 06:14:11 -07:00 |
|
bbracker
|
e0b6566cbd
|
buildroot do scripts now compile flops
|
2021-10-23 23:14:59 -07:00 |
|
bbracker
|
26eead1c77
|
add W stage signals to linux testbench
|
2021-10-23 14:00:53 -07:00 |
|
bbracker
|
de6a52f6eb
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-10-23 13:17:37 -07:00 |
|
bbracker
|
3c0b0987d2
|
add option for regression to do a partial execution of buildroot
|
2021-10-23 13:17:30 -07:00 |
|
David Harris
|
200eb453fb
|
wrapping up lint cleanup; many unused signals removed
|
2021-10-23 12:15:14 -07:00 |
|
David Harris
|
c9e9cd4a60
|
more lsu/ifu lint cleanup
|
2021-10-23 12:10:13 -07:00 |
|
David Harris
|
2cfbd888fd
|
more lsu/ifu lint cleanup
|
2021-10-23 12:00:32 -07:00 |
|
David Harris
|
62a23fe878
|
lsu/ifu lint cleanup
|
2021-10-23 11:41:20 -07:00 |
|
David Harris
|
61fdb3d902
|
random lint cleanup
|
2021-10-23 11:24:36 -07:00 |
|
David Harris
|
8d9efcbafb
|
IEU cleanup
|
2021-10-23 11:13:28 -07:00 |
|
David Harris
|
4bf823e063
|
lint cleanup
|
2021-10-23 11:03:28 -07:00 |
|
David Harris
|
d570df864f
|
IEU lint cleanup
|
2021-10-23 10:51:53 -07:00 |
|
David Harris
|
8e516e6391
|
Lint cleanup from wallypipeliendhart
|
2021-10-23 10:29:52 -07:00 |
|
David Harris
|
33358d101e
|
Lint cleanup: ahblite, ifu, hart
|
2021-10-23 10:12:33 -07:00 |
|
David Harris
|
d24bece3a8
|
Lint cleanup
|
2021-10-23 09:58:52 -07:00 |
|
David Harris
|
2e796e3da2
|
lint cleanup: FPU and privileged
|
2021-10-23 09:41:24 -07:00 |
|
David Harris
|
c316bff15a
|
subword read and csrc lint cleanup
|
2021-10-23 09:29:15 -07:00 |
|
David Harris
|
28d8f6d5cf
|
FMA and CSRC lint cleanup
|
2021-10-23 09:20:24 -07:00 |
|
David Harris
|
11b0607e63
|
Lint cleanup
|
2021-10-23 09:06:21 -07:00 |
|
David Harris
|
ac1b1bfbb6
|
update scripts for handling src/*/* subdirectories
|
2021-10-23 08:54:29 -07:00 |
|
David Harris
|
0dabb6ebd4
|
lint cleaning and moved files into subdirectories
|
2021-10-23 08:53:32 -07:00 |
|
David Harris
|
f483e8002a
|
Lint cleanup
|
2021-10-23 08:39:21 -07:00 |
|
David Harris
|
e2e950ac0f
|
Cleaned up LINT erors
|
2021-10-23 06:28:49 -07:00 |
|
David Harris
|
4c480a40f6
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-10-23 06:15:49 -07:00 |
|
David Harris
|
3249d65209
|
Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience.
|
2021-10-23 06:15:26 -07:00 |
|
kipmacsaigoren
|
ef297067e9
|
removed reduntant definitions for FPU in MISA.
|
2021-10-22 15:18:25 -05:00 |
|
James E. Stine
|
f6e8e45901
|
Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking
|
2021-10-22 13:41:50 -05:00 |
|
Katherine Parry
|
7c7c0f538a
|
put the FMA priority encoders into their own module
|
2021-10-22 10:03:12 -07:00 |
|
James E. Stine
|
0dcca43f48
|
Get rid of lint warning - still need more testing though
|
2021-10-21 15:19:22 -05:00 |
|
James E. Stine
|
dd7dbaa382
|
Clean up some FPU and add pipelined fpdivsqrt to fpu.sv
|
2021-10-21 13:52:12 -05:00 |
|
James E. Stine
|
bafb3a983d
|
Fix fpdivsqrt lint error on CPA for convergence
|
2021-10-20 17:46:13 -05:00 |
|
David Harris
|
ceaf84a3ce
|
removed .* from wallypipeliendsoc
|
2021-10-20 13:49:18 -07:00 |
|
James E. Stine
|
71b48048da
|
Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits.
|
2021-10-20 12:00:41 -05:00 |
|
David Harris
|
47e19d4caa
|
moved coemark and testsBP to tests
|
2021-10-20 09:10:06 -07:00 |
|
David Harris
|
23b3d7dbc1
|
Move tests into subdirectory and moved wavedrom out of project
|
2021-10-20 09:03:21 -07:00 |
|
David Harris
|
a88af1841f
|
radix 2 SRT checkin
|
2021-10-19 14:08:16 -07:00 |
|
James E. Stine
|
41010aa418
|
Some more sanitization but will pass to legal to determine if okay on version - it is substantially different in some ways but not a legal expert on this
|
2021-10-19 12:09:43 -05:00 |
|
James E. Stine
|
a75abb04bd
|
Modify DW02_multp to properly list the correct number of bits at the output (i.e., 2*WIDTH + 2).
|
2021-10-19 11:58:06 -05:00 |
|
David Harris
|
3bc985d230
|
Changed some flops to settable
|
2021-10-18 17:05:29 -07:00 |
|
David Harris
|
0516ee768b
|
replaced flopenl with flopenr when clearing to 0
|
2021-10-18 16:53:18 -07:00 |
|
David Harris
|
398337951d
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-10-18 15:44:31 -07:00 |
|
David Harris
|
00d8035836
|
Fixed multiplier and pointed arch tests to new path in addins
|
2021-10-18 15:43:59 -07:00 |
|
Ross Thompson
|
cd58a388e4
|
fixed issues with dc shell not liking modules with parameters without default values.
|
2021-10-18 17:24:15 -05:00 |
|
James E. Stine
|
37fe5e56a8
|
Sanitization some more on mult_cs.sv
|
2021-10-18 05:24:16 -05:00 |
|
James E. Stine
|
d0ab43e4e8
|
Update some on mult_cs and delete DW02_mult.v
|
2021-10-18 05:06:49 -05:00 |
|
James E. Stine
|
de7b673e34
|
Add hacky hand-made carry/save multiplier - will improve
|
2021-10-16 10:37:29 -05:00 |
|
Katherine Parry
|
c34633804a
|
cvtfp module documented
|
2021-10-14 15:25:31 -07:00 |
|