bbracker
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23194c0308
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fix parseState.py to correctly take in PMPCFG
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2021-11-24 16:52:51 -08:00 |
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Ross Thompson
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1183aed049
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Missed another change to uart.
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2021-11-23 10:20:47 -06:00 |
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Ross Thompson
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3fc370654d
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Fixed syntax error which modelsim did not detect in my changes for making uart work with qemu's simulation.
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2021-11-23 10:00:32 -06:00 |
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Ross Thompson
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f12e7e1b68
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Added QEMU hack for initial LCR value in uart.
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2021-11-22 15:23:19 -06:00 |
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Ross Thompson
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f05a66acd1
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Hack added to uart so QEMU simulation can work with an ultra fast baud rate relative to the clock speed.
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2021-11-22 15:20:54 -06:00 |
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Ross Thompson
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d5cf6da6eb
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-11-22 11:30:14 -06:00 |
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bbracker
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cffb72042a
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activate STVAL for buildroot
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2021-11-21 10:40:28 -08:00 |
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Ross Thompson
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e955b17500
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-11-20 22:44:45 -06:00 |
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Ross Thompson
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055a5bd202
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Removed unneeded check for icache ways.
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2021-11-20 22:44:37 -06:00 |
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Ross Thompson
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9d3261ed49
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Reversed bit order in uart.
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2021-11-20 22:43:05 -06:00 |
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Ross Thompson
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88b4e0946f
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-11-20 22:37:15 -06:00 |
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Ross Thompson
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705572f0ac
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Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.
If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
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2021-11-20 22:35:47 -06:00 |
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bbracker
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4e96d0f1db
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add checkpoints to regression
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2021-11-20 19:42:53 -08:00 |
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bbracker
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e5d3416258
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-11-19 20:25:06 -08:00 |
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bbracker
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713aa7faac
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automatic bug finder script
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2021-11-19 20:25:00 -08:00 |
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bbracker
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c07caf4fe8
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increase buildroot progress expecttions; increase timeout to 20 hours
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2021-11-19 12:52:11 -08:00 |
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David Harris
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82cfebfb83
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Coremark Cleanup, trying compile from addins
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2021-11-19 06:09:04 -08:00 |
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David Harris
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a801e0dbec
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Moved exe2memfile.pl
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2021-11-18 20:32:13 -08:00 |
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David Harris
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690410721d
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Cleaning up CoreMark benchmark
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2021-11-18 20:12:52 -08:00 |
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David Harris
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8e8b84f532
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vert "Simplifying riscv-coremark"
This reverts commit ce8232e396.
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2021-11-18 18:40:13 -08:00 |
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David Harris
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ce8232e396
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Simplifying riscv-coremark
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2021-11-18 17:15:40 -08:00 |
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David Harris
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b73e6354e3
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-11-18 16:14:42 -08:00 |
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David Harris
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402b473dbb
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CoreMark testing
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2021-11-18 16:14:25 -08:00 |
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slmnemo
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0bf1836a3a
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Removed .* from hazard hzu(.*).
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2021-11-17 14:21:23 -08:00 |
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slmnemo
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5c28553ca1
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Removed .* from hazard hzu(.*) in wallypipelinedhart.sv.
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2021-11-17 14:08:08 -08:00 |
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slmnemo
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df6c54a664
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-11-17 13:38:51 -08:00 |
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slmnemo
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bf8cef78bc
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removed .* from muldiv.sv (REAL)
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2021-11-17 13:37:50 -08:00 |
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David Harris
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0a281a06e0
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-11-17 13:28:33 -08:00 |
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Noah Limpert
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b63c0f35d1
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ieu variable naming changed for clarity
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2021-11-17 13:24:28 -08:00 |
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slmnemo
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c5c886ddc1
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-11-17 13:23:20 -08:00 |
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slmnemo
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40efffc70b
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Removed .*s from muldiv.sv
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2021-11-17 13:23:12 -08:00 |
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Noah Limpert
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bbd17e730b
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-11-17 13:04:33 -08:00 |
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Noah Limpert
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70a84b56c8
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Updated IFU variable naming for clarity
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2021-11-17 12:39:05 -08:00 |
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Kevin Kim
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6437c04074
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-11-17 12:18:25 -08:00 |
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Kevin Kim
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38437c664e
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root level makefile added
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2021-11-17 12:17:56 -08:00 |
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Kip Macsai-Goren
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7a8c21e71f
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renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv
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2021-11-17 10:53:17 -08:00 |
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Skylar Litz
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6fde97b16c
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fixed interrupt timing bug
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2021-11-16 16:46:17 -08:00 |
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David Harris
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c610be25a7
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-11-16 12:30:55 -08:00 |
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bbracker
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2203590f9f
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get current privilege level from GDB for checkpoints
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2021-11-15 14:49:00 -08:00 |
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Skylar Litz
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3dd83b3113
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fix timing of delayed interrupt
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2021-11-11 09:35:51 -08:00 |
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David Harris
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570f24a9e4
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bringing Coremark back to life
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2021-11-10 12:43:31 -08:00 |
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Kevin Kim
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7cb8b76ef6
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Makefile added in regression directory:
-cd's into imperas then runs make commands, finally running the tvLinker script
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2021-11-09 10:55:48 -08:00 |
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bbracker
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f6a555009b
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increase expectations for buildroot and timeout count
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2021-11-06 14:57:29 -07:00 |
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bbracker
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c92d41a597
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checkpoint MIDELEG support
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2021-11-06 03:44:23 -07:00 |
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bbracker
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bc6332a780
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fix merge conflict
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2021-11-05 23:42:15 -07:00 |
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bbracker
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17e776f853
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checkpoints now use binary ram files
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2021-11-05 22:37:05 -07:00 |
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Kevin
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11efaa2669
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changed code aligner to run recursively on a root directory
-only runs the aligner on .sv files
-runs recursively on sub-directories
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2021-11-03 10:49:34 -07:00 |
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bbracker
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0c7681b942
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fix testbench interrupt timing
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2021-11-02 21:19:12 -07:00 |
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bbracker
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526aff54a8
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linux testgen refactor
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2021-11-01 14:09:49 -07:00 |
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David Harris
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d7f0abca5a
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Add3d wally32i test
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2021-11-01 13:17:49 -07:00 |
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