Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity
6,101 Commits 14 Branches 1 Tag 31 MiB
param
Commit Graph

440 Commits

Author SHA1 Message Date
David Harris
1d3b41e0fb New expression for BTB_SIZE to avoid error during sky90 synthesis 2023-02-20 04:02:00 -08:00
Ross Thompson
2d417c33a4 Simplified BTB by removing the valid bit. the instruction class provides the equivalent information. 2023-02-19 23:53:20 -06:00
Ross Thompson
0d79c0cebe Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-19 22:54:27 -06:00
Ross Thompson
b32093b33b Simplified branch predictor. 2023-02-19 22:49:48 -06:00
David Harris
0ac9c9e62a Added BTB_SIZE parameter independent of BPRED_SIIZE 2023-02-19 20:13:50 -08:00
David Harris
5b197f4f9d Parameterized btb to depend on BPRED_SIZE 2023-02-19 19:59:07 -08:00
Kip Macsai-Goren
8d0a600b96 Merge remote-tracking branch 'upstream/main' into main 2023-02-19 16:37:18 -08:00
David Harris
06872e3822 Adjusted DTIM to always be 512B independent of XLEN 2023-02-19 16:14:38 -08:00
David Harris
5b8d1e4134 PMP checker size check to avoid spurious warnings 2023-02-19 16:08:23 -08:00
David Harris
ac21bed64d Moved conditional instantiation outside pmpchecker 2023-02-19 15:31:00 -08:00
David Harris
7d031fcae0 Disabled W64M register for RV32 2023-02-19 07:03:31 -08:00
David Harris
6d405ad69b Fixed RAM instantiations 2023-02-19 06:31:41 -08:00
Ross Thompson
9ee48637dc Possibly much better branch predictor implemention. 
The complexity is significantly reduced.
 2023-02-19 00:17:37 -06:00
Kevin Kim
2069d92f9e B DONE (for now) 
- datapath passes along comparator flag to alu
-  controllers and zbb handle min/max instructions
 2023-02-18 22:12:55 -08:00
Ross Thompson
d44cb1febb Minor fix. 2023-02-18 23:55:46 -06:00
Kevin Kim
888f4318bc controlleres and zbb handle byte instructions 2023-02-18 21:06:55 -08:00
Kevin Kim
27581f8d28 alu and controllers handle andn, orn, xnor 2023-02-18 20:57:07 -08:00
Kevin Kim
ba968ed95e added logic to handle sign/zero extend instructions 2023-02-18 20:32:40 -08:00
Kevin Kim
5c563bef43 fixed ctlzw bug in count unit 2023-02-18 20:12:30 -08:00
Kevin Kim
6d60268240 zbb handles count instructions 2023-02-18 20:12:17 -08:00
Kevin Kim
9760f0ccfd fixed bmuctrl decode bug 2023-02-18 20:11:50 -08:00
Kevin Kim
84ddb6fb54 updated comments in bmuctrl 2023-02-18 19:57:10 -08:00
Kevin Kim
bec2905ee5 rotate instructions now handled in ZBB unit 2023-02-18 19:56:54 -08:00
Kevin Kim
e47cc222a6 removed redundant decode logic in bmuctrl 2023-02-18 19:50:36 -08:00
Kevin Kim
9203b0cc2f began ZBB integration into ieu 2023-02-18 19:44:14 -08:00
Kevin Kim
7780cbd47a bmuctrl handles roriw 2023-02-18 16:26:16 -08:00
Kip Macsai-Goren
883a6ca005 merge upstream synth changes 2023-02-18 14:35:19 -08:00
David Harris
0eda753dc4 Removed unused PredInstrClassE register from bpred 2023-02-18 05:59:25 -08:00
David Harris
0f4226a950 Removed unused weq0M register fron fdivsqrtpostproc 2023-02-18 05:57:39 -08:00
David Harris
66e5c60fb4 Fixed issue #57 of sign selection for improperly NaN-boxed number 2023-02-18 05:34:40 -08:00
David Harris
5986931fdc Fixed unpacking of illegal NaN box. Fixed issue #56 of sign injection NaN 2023-02-18 05:25:38 -08:00
Kevin Kim
92c0d3a4ed configured shifter in alu 2023-02-17 21:58:49 -08:00
Kevin Kim
182b27dfc8 shifter bug fix 
- roli not passing unless I keep the MSB (instead of inverting) of truncated offset
 2023-02-17 21:58:26 -08:00
Kevin Kim
c353378da8 controller supports some rotates 2023-02-17 21:57:34 -08:00
Kevin Kim
4a52b57002 bmuctrl supports some rotates 2023-02-17 21:57:19 -08:00
David Harris
dc19f8a8ec Created PostBox signal to NaN-box malformed NaNs of excess length. Fixes Issue #55 2023-02-17 20:51:43 -08:00
Kevin Kim
50ec6baa07 added zero extend, pre-shift mux to ALU 2023-02-17 20:15:12 -08:00
Kevin Kim
e2d90a9422 more elegant ZBA logic in controller 2023-02-17 20:14:47 -08:00
Kevin Kim
cd92d6e5d1 bmuctrl handles .uw instructions 2023-02-17 20:14:13 -08:00
David Harris
a194740562 Fixed RAM bugs and refactored with read taking place after clock edge rather than before. 2023-02-17 19:14:38 -08:00
Kevin Kim
750882455f controller supports ZBA instructions 2023-02-17 16:44:16 -08:00
Kevin Kim
fcae58fcc7 removed Funct7 in Execute Stage 2023-02-17 16:12:09 -08:00
David Harris
9275bfb839 Memory synthesis updates 2023-02-17 15:33:49 -08:00
David Harris
2060683770 Continue fixing memory macros for synthesis 2023-02-17 15:15:37 -08:00
Ross Thompson
0cacfbd322 Renamed globalhistory predictor. 2023-02-17 16:08:34 -06:00
Ross Thompson
2f1bebfd57 Fixed global history predictor. 2023-02-17 16:05:48 -06:00
Ross Thompson
a95be0b567 More updates. 2023-02-17 15:53:49 -06:00
Ross Thompson
df4a27a2e3 Updated global history predictor. 2023-02-17 15:53:15 -06:00
David Harris
3523318acb Synthesis with memories 2023-02-17 13:51:05 -08:00
Ross Thompson
0d271130b9 Fixed a branch predictor performance issue. 2023-02-17 15:37:03 -06:00
Kevin Kim
9bf11471aa bmuctrl checks for illegal zbs-style instructions 2023-02-17 12:54:08 -08:00
Kevin Kim
0bab3bec3d bctrl bug fix 
- bctrl decodes shift immediate instructions properly
 2023-02-17 11:16:29 -08:00
Kevin Kim
bb79b57cc1 alu bug fix 
- condmaskb piped in correctly instead of b
 2023-02-17 11:02:07 -08:00
Kevin Kim
ee3a520a1f alu looks at BSelect, added BSelect one hot signal 2023-02-17 09:51:49 -08:00
Ross Thompson
5d5e4580d4 Merge branch 'main' of github.com:ross144/cvw 2023-02-17 10:58:16 -06:00
Ross Thompson
a325adf1be Fixed bug with branch predictor. 2023-02-17 10:57:50 -06:00
Kevin Kim
890c54bc0b added alu changes to previous commit 2023-02-17 08:22:13 -08:00
Kevin Kim
ec2421ead4 added BSelect Signal 
- BSelect [3:0] is a one hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
 2023-02-17 08:21:55 -08:00
Kevin Kim
81cb00aaee comments 2023-02-17 07:53:14 -08:00
Kevin Kim
505f3bf42f comments 2023-02-17 07:52:54 -08:00
Kevin Kim
256d362e0d comment formatting 2023-02-17 07:51:28 -08:00
Kevin Kim
9ab8183e80 alu handles ALU select instead of funct3 2023-02-17 07:51:10 -08:00
Kevin Kim
9128ac5409 added BMU controll 2023-02-17 07:50:59 -08:00
Kevin Kim
25c0811d3d Added ALUSelect signal into datapath, ieu, controller 2023-02-17 07:50:45 -08:00
David Harris
c3cc2f98d6 Reverted lab3 changes in dev branch 2023-02-16 18:10:05 -08:00
David Harris
5fef9de80e Merge branch 'lab3_2023' of https://github.com/openhwgroup/cvw into dev 2023-02-16 17:57:51 -08:00
David Harris
532abb5b95
Update datapath.sv 2023-02-16 17:53:31 -08:00
David Harris
6527257305
Update controller.sv 2023-02-16 17:52:44 -08:00
David Harris
685d3ff568
Update alu.sv 2023-02-16 17:52:25 -08:00
Ross Thompson
27f6552315 keep this commit off of cvw. 2023-02-16 11:05:24 -06:00
David Harris
d83c61cafc Added SSTC support for supervisor timer compare, but presently disable support. Reenable for rv32gc and rv64gc after tests pass. 2023-02-16 07:37:12 -08:00
Kevin Kim
465aad372a added comments to zbc units 2023-02-15 17:42:32 -08:00
Kevin Kim
aad4d13603 zbc configurability and select mux 2023-02-15 17:39:37 -08:00
Kevin Kim
068ddc3e0d controller forwards funct7 
- started the bmu controll register
 2023-02-15 17:38:12 -08:00
Kevin Kim
6ac54a180e zbc and carry-less multiply work properly 2023-02-15 17:37:09 -08:00
James Stine
744991bd5a Update if-then-else for ram items 2023-02-15 18:12:12 -06:00
Kevin Kim
cf8392cbd8 continued ZBC integration into ALU 2023-02-15 09:35:07 -08:00
Ross Thompson
69472b8145 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-15 11:29:39 -06:00
Kevin Kim
5426dd6184 added ALUResult Signal 2023-02-15 09:13:10 -08:00
Kevin Kim
9cec59ea2c controller passes funct7 from decode to execute 2023-02-14 16:06:10 -08:00
Kevin Kim
70f2dd701c git 2023-02-14 16:03:26 -08:00
Kevin Kim
9728e00dfd Merge branch 'tmp' into main 2023-02-14 13:12:57 -08:00
Kevin Kim
85c2ed8d34 removed unncessary stuff 2023-02-14 13:07:03 -08:00
Kevin Kim
8e371864e4 reverted back to I tests working 2023-02-14 13:06:31 -08:00
Kevin Kim
fd46e0080c added ALU result select mux for B instructions 2023-02-13 17:38:00 -08:00
Kevin Kim
84ca2cab9c controller handles bclr 2023-02-13 16:57:05 -08:00
Ross Thompson
094b307724 Merge branch 'main' of github.com:ross144/cvw 2023-02-13 18:54:07 -06:00
Ross Thompson
9c9acc0055 Updated gshare (no speculation) to have better performance. 2023-02-13 18:52:52 -06:00
Kevin Kim
29abec2409 Shadd instructions pass tests 2023-02-13 16:36:17 -08:00
Ross Thompson
33d2bf84f8 More fixeds to global history. 2023-02-13 18:08:51 -06:00
Ross Thompson
a579bbcdd1 Fixed global history predictor. 2023-02-13 18:08:13 -06:00
Ross Thompson
bbc6095260 Updated global history predictor. 2023-02-13 18:07:32 -06:00
Ross Thompson
9f25b53b36 Fixed bug in basic gshare implementation. Should be a better comparison to the speculative versions now. 2023-02-13 17:57:05 -06:00
Ross Thompson
b298a8afc5 Created copy of gshare. I think there may be a simpler implementation. 2023-02-13 17:29:51 -06:00
Ross Thompson
a80dbd3aec Further branch predictor improvements. 2023-02-13 17:23:56 -06:00
Ross Thompson
717cba270c Partial improvement. 2023-02-13 17:10:24 -06:00
Ross Thompson
f4af38a004 Hacked commit. Fixes the gshare bugs introduced last week. 
Need to recover the good changes in the next commit.
 2023-02-13 16:14:17 -06:00
Kevin Kim
27223a05e2 ALU lint fixes 2023-02-13 14:01:51 -08:00
Kevin Kim
29d03dbfc7 ALU configurability changes 
-stuff that was ZBA supported was in ZBB so I changed that
 2023-02-13 14:00:06 -08:00
Kevin Kim
12911440d0 edited controller so that add.uw passes tests 2023-02-13 13:49:46 -08:00
Kevin Kim
7eb41058c7 alu add.uw needs w64 to be false 2023-02-13 13:49:35 -08:00
Ross Thompson
1d74663f42 Partial fix for gshare bugs from the last two weeks. 2023-02-13 11:57:25 -06:00
Ross Thompson
58749a8c57 Removed another bit from btb class. 2023-02-12 11:33:43 -06:00
Kevin Kim
31787c456b simulation runs-- clmul doesn't pass lint with xor tree 2023-02-11 21:22:33 -08:00
Kevin Kim
5f08322e99 lint fixes 2023-02-11 21:13:10 -08:00
Kevin Kim
6a7fe6352e zbb, zbs, cnt lint fixes 2023-02-11 20:41:52 -08:00
Kevin Kim
61b46e0639 fixed byte unit lints 2023-02-11 20:25:34 -08:00
Kevin Kim
fb99bdab82 fixed lints in cnt 2023-02-11 20:22:42 -08:00
Kevin Kim
c59dfc1e30
fixed typo in LZC 2023-02-11 19:59:03 -08:00
Kevin Kim
38087be3b7 popcnt passes lint 2023-02-11 19:19:38 -08:00
Kevin Kim
76bc1b5999 clmul passes lint 2023-02-11 19:16:13 -08:00
Ross Thompson
1e0667db1d More simplifications to the BP. 2023-02-10 17:09:35 -06:00
Ross Thompson
9c4da7381f Experimental branch prediction optimization. 2023-02-10 15:45:56 -06:00
Kip Macsai-Goren
a7237baa87 fixed small errors to get regression to run with bit manip supported. 2023-02-10 10:37:06 -08:00
Kip Macsai-Goren
f91d74896a Merge remote-tracking branch 'upstream/main' into main 2023-02-10 10:01:14 -08:00
Ross Thompson
9c2e0de672 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-10 10:38:39 -06:00
Ross Thompson
c229f0064e Modified branch predictor to use InstrValidE and InstrValidD rather than the more complex InstrClassE | WrongClassE logic. 2023-02-10 10:33:10 -06:00
Ross Thompson
282ffd1313 RAS and RAS documentation now consistent. 2023-02-10 09:06:51 -06:00
Ross Thompson
faf7cd8c8a Updated globalhistory predictor. 2023-02-09 14:48:02 -06:00
Kevin Kim
726722bec2 Include Funct7 in execute 
- Modifed datapath to support funct7 in execute
- Modified controller to pass on Funct7
- all lints pass
 2023-02-09 19:18:54 +00:00
Kevin Kim
847a4145f1 added W64 zbb input signal in alu 2023-02-09 19:07:22 +00:00
Kevin Kim
e4bfa4c548 modified zbb to account for cnt module change 2023-02-09 16:45:37 +00:00
Kevin Kim
ce9dca8aec modified cnt for zbb to mux inputs 2023-02-09 16:45:22 +00:00
Ross Thompson
996bb289d3 Simplified branch predictor. 2023-02-08 18:24:38 -06:00
Kevin Kim
95ff9e91c5 moved files into bmu folder 2023-02-08 13:57:09 +00:00
Kip Macsai-Goren
0dad7bf114 Merge remote-tracking branch 'upstream/main' into main 2023-02-07 23:28:50 -08:00
David Harris
5bf709d7c3 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-02-07 16:49:58 -08:00
Ross Thompson
7263fab4b1 Branch predictor cleanup. 2023-02-07 14:01:59 -06:00
David Harris
195e7c1a9c Moved STATUS_FS_INT write to if statement to properly prioritize 2023-02-07 06:55:42 -08:00
David Harris
0712fa8f67 Disabled STATUS_FS at reset, fixing issue #71 2023-02-07 06:31:14 -08:00
Kip Macsai-Goren
7198592afc fixed merge conflicts with removal of pipelined folder 2023-02-06 18:04:28 -08:00
Ross Thompson
54a128491e Fixed Bug 66. 
If a load missed at the same time as a spilled instruction fetch with an ITLB miss in the second cache line, the HPTW did not wait for the load miss to finish.
 2023-02-06 17:32:28 -06:00
Ross Thompson
a33c579e4b Removed unreachable if branch in hptw next state logic. 2023-02-06 16:42:07 -06:00
David Harris
103781923e Parenthesized reduction operators to avoid DC lint 2023-02-04 18:49:47 -08:00
David Harris
1bb5599806 Developing debug test 2023-02-04 08:31:47 -08:00
David Harris
b13087e706 Fixed merge issues on synthDC PR 2023-02-04 04:13:40 -08:00
David Harris
e0915acad9 Improved illegal NaN-box detection and formatted fsgninj 2023-02-04 03:42:20 -08:00
David Harris
d7ae05ae8e Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-02-03 08:36:11 -08:00
David Harris
aae035226f Merged with memories 2023-02-02 14:50:46 -08:00
David Harris
99d179dd3e Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00