David Harris
58ac237817
rv32e starting to use parameters
2023-04-14 13:29:39 -07:00
David Harris
ab7ea93425
param update
2023-04-05 13:19:20 -07:00
David Harris
301d13d027
param branch passes lint and sim
2023-04-04 11:36:27 -07:00
David Harris
5fbd9d7204
parameterized upper level modules and uncore; not yet working with uncore
2023-04-03 06:11:55 -07:00
David Harris
d8f6b9e15e
paramterized wally32e passes lint and sim
2023-03-31 12:00:44 -07:00
David Harris
193061cb3c
Merge branch 'dev' into param
2023-03-31 11:30:53 -07:00
David Harris
03b4f6660c
Coverage improvement: ieu, hazard, priv
2023-03-31 08:34:34 -07:00
David Harris
b95730e3a1
Coverage improvements in ieu, hazard units
2023-03-31 08:33:46 -07:00
Marcus Mellor
984d4b9918
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-03-31 10:29:10 -05:00
Mike Thompson
a28a457099
Merge pull request #179 from davidharrishmc/dev
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Fixed broken regression: privileged tests and build root
2023-03-31 10:56:27 -04:00
Marcus Mellor
c7ec42eaab
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-03-31 09:54:02 -05:00
Marcus Mellor
913cdecb65
Address comments in openhwgroup/cvw#180
2023-03-31 09:51:33 -05:00
Kevin Kim
97181e063b
only pass in relevant comparator flag to ALU
2023-03-30 19:15:33 -07:00
Kevin Kim
bd1ac13f5f
Merge branch 'bitmanip_cleanup' of https://github.com/kipmacsaigoren/cvw into bitmanip_cleanup
2023-03-30 19:04:41 -07:00
Kevin Kim
b43e4d8d0d
Merge branch 'openhwgroup:main' into bitmanip_cleanup
2023-03-30 19:04:36 -07:00
Marcus Mellor
64f15d48de
Disable coverage for branches tested in fpu.s
2023-03-30 19:44:55 -05:00
David Harris
77d5f1c81b
Refactored InstrValidNotFlushed into CSR Write signals
2023-03-30 17:06:09 -07:00
David Harris
25cd1cc432
Started factoring out InstrValidNotFlushed from CSRs
2023-03-30 14:56:19 -07:00
David Harris
a4ae1b9cbb
fctrl updated and buildroot working again
2023-03-30 13:17:15 -07:00
David Harris
fc01f45c80
fctrl continued cleanup
2023-03-30 13:07:39 -07:00
David Harris
e68e473da9
fctrl continued cleanup
2023-03-30 13:05:56 -07:00
David Harris
b07c71ea41
Started to clean up fctrl
2023-03-30 12:57:14 -07:00
Kip Macsai-Goren
94f03b0d78
unnecessary comments cleanup
2023-03-29 19:32:57 -07:00
Kip Macsai-Goren
da905b4eb9
Resolved ImperasDV receiving incorrect cause values
2023-03-29 15:04:56 -07:00
David Harris
de2a0da9e9
Reduced number of bits in mcause and medeleg registers
2023-03-29 07:02:09 -07:00
David Harris
96e3c3bea8
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-03-29 06:19:10 -07:00
David Harris
043e4fe5f4
Simplified fctrl
2023-03-28 21:13:48 -07:00
Alec Vercruysse
bfb4f0d6eb
add check for legal funct3 for IW instructions
2023-03-28 15:59:48 -07:00
David Harris
77affa7ccd
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-03-28 14:33:18 -07:00
Ross Thompson
73e6972f0b
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-03-28 16:31:50 -05:00
David Harris
5e352bf72e
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-03-28 14:27:08 -07:00
Ross Thompson
69f6b291c6
Possible fix for issue 148.
...
I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU.
I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss.
This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works.
2023-03-28 14:47:08 -05:00
Kevin Kim
adabb7c236
comment formatting
2023-03-28 11:40:19 -07:00
Kevin Kim
4c9670a082
Merge branch 'openhwgroup:main' into bitmanip_cleanup
2023-03-28 11:31:18 -07:00
David Harris
f0cab709f2
Added support (untested) for half and quad conversions
2023-03-28 10:53:06 -07:00
David Harris
40311c4f62
fixed fp->fp conversions
2023-03-28 10:35:41 -07:00
David Harris
e5955c5dd8
support more fp -> fp conversions
2023-03-28 10:28:01 -07:00
David Harris
fd2d08f501
Fixed fmv decoder
2023-03-28 10:21:33 -07:00
Ross Thompson
d55b0c8c1f
Merge pull request #169 from davidharrishmc/dev
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PMP Fix to issue 132
2023-03-28 11:49:00 -05:00
David Harris
aa31b45d88
Fixed RV32 tests after PMP fix
2023-03-28 08:35:23 -07:00
David Harris
39d3bf8e8a
Fixed PMP issue 132. Updated tests to initialize PMP before using. Needs to remake tests
2023-03-28 06:58:17 -07:00
David Harris
20ebf7e536
CSRS privileged coverage test
2023-03-28 04:37:56 -07:00
Ross Thompson
8504774a11
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-03-27 11:55:19 -05:00
David Harris
edaa306240
Removed unnecessary monitor
2023-03-27 09:52:38 -07:00
Ross Thompson
88c572d9bb
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-03-27 10:22:48 -05:00
Lee Moore
39ac6be103
Merge branch 'openhwgroup:main' into add-linux
2023-03-27 09:44:13 +01:00
Kevin Kim
f3edbcea15
removed unnecessary signal indices
2023-03-26 20:06:55 -07:00
Kevin Kim
b4d6021b3b
removed unneccesary input signal from zbb
2023-03-26 19:39:49 -07:00
Ross Thompson
3fc0c4b34e
Modified plic and uart to remove async reset. This removes vivado critical warning.
2023-03-24 20:37:48 -05:00
Ross Thompson
78ab9f59af
Updated GPIO signal names to reflect book.
2023-03-24 18:55:43 -05:00
