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cvw/wally-pipelined/testbench/testbench-imperas.sv

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Initial Checkin
2021-01-15 04:37:51 +00:00
///////////////////////////////////////////
Added test configurations
2021-01-25 16:28:43 +00:00
// testbench-imperas.sv
Initial Checkin
2021-01-15 04:37:51 +00:00
//
// Written: David_Harris@hmc.edu 9 January 2021
// Modified:
//
// Purpose: Wally Testbench and helper modules
Added test configurations
2021-01-25 16:28:43 +00:00
// Applies test programs from the Imperas suite
Initial Checkin
2021-01-15 04:37:51 +00:00
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
Replaced parameters with macros for XLEN, MISA, other configuration, and renamed wally-params.sv to wally-config.vh
2021-01-23 15:48:12 +00:00
`include "wally-config.vh"
Initial Checkin
2021-01-15 04:37:51 +00:00
Replaced parameters with macros for XLEN, MISA, other configuration, and renamed wally-params.sv to wally-config.vh
2021-01-23 15:48:12 +00:00
module testbench();
Fixed the issue with the batch mode not working after adding the function radix.
2021-03-13 02:16:03 +00:00
parameter DEBUG = 0;
working testbench-imperas
2021-05-04 02:16:58 +00:00
parameter TESTSPERIPH = 0; // set to 0 for regression
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
2021-05-29 03:11:37 +00:00
parameter TESTSPRIV = 0; // set to 0 for regression
Added debug option to disable the function radix if not needed. Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
2021-03-10 21:17:02 +00:00
Initial Checkin
2021-01-15 04:37:51 +00:00
logic clk;
logic reset;
updated pipeline tests
2021-05-04 02:07:36 +00:00
parameter SIGNATURESIZE = 5000000;
Initial Checkin
2021-01-15 04:37:51 +00:00
int test, i, errors, totalerrors;
working testbench-imperas
2021-05-04 02:16:58 +00:00
logic [31:0] sig32[0:SIGNATURESIZE];
logic [`XLEN-1:0] signature[0:SIGNATURESIZE];
Replaced parameters with macros for XLEN, MISA, other configuration, and renamed wally-params.sv to wally-config.vh
2021-01-23 15:48:12 +00:00
logic [`XLEN-1:0] testadr;
Initial Checkin
2021-01-15 04:37:51 +00:00
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-30 19:25:07 +00:00
logic [31:0] InstrW;
Replaced parameters with macros for XLEN, MISA, other configuration, and renamed wally-params.sv to wally-config.vh
2021-01-23 15:48:12 +00:00
logic [`XLEN-1:0] meminit;
Update virtual memory tests and move to separate folder
2021-03-31 02:18:29 +00:00
Progress towards the test bench flush.
2021-07-12 19:22:13 +00:00
string tests32mmu[] = '{
"rv32mmu/WALLY-MMU-SV32", "3000"
};
Update virtual memory tests and move to separate folder
2021-03-31 02:18:29 +00:00
Progress towards the test bench flush.
2021-07-12 19:22:13 +00:00
string tests64mmu[] = '{
"rv64mmu/WALLY-MMU-SV48", "3000",
"rv64mmu/WALLY-MMU-SV39", "3000"
};
Update virtual memory tests and move to separate folder
2021-03-31 02:18:29 +00:00
floating point infinite loop removed from imperas tests
2021-05-18 14:42:51 +00:00
string tests32f[] = '{
"rv32f/I-FADD-S-01", "2000",
"rv32f/I-FCLASS-S-01", "2000",
Fixed writting MStatus FS bits
2021-07-13 17:20:30 +00:00
"rv32f/I-FCVT-S-W-01", "2000",
"rv32f/I-FCVT-S-WU-01", "2000",
"rv32f/I-FCVT-W-S-01", "2000",
"rv32f/I-FCVT-WU-S-01", "2000",
FDIV and FSQRT passes when simulating in modelsim
2021-07-19 03:00:04 +00:00
"rv32f/I-FDIV-S-01", "2000",
floating point infinite loop removed from imperas tests
2021-05-18 14:42:51 +00:00
"rv32f/I-FEQ-S-01", "2000",
"rv32f/I-FLE-S-01", "2000",
"rv32f/I-FLT-S-01", "2000",
"rv32f/I-FMADD-S-01", "2000",
"rv32f/I-FMAX-S-01", "2000",
"rv32f/I-FMIN-S-01", "2000",
"rv32f/I-FMSUB-S-01", "2000",
"rv32f/I-FMUL-S-01", "2000",
"rv32f/I-FMV-W-X-01", "2000",
"rv32f/I-FMV-X-W-01", "2000",
"rv32f/I-FNMADD-S-01", "2000",
"rv32f/I-FNMSUB-S-01", "2000",
"rv32f/I-FSGNJ-S-01", "2000",
"rv32f/I-FSGNJN-S-01", "2000",
"rv32f/I-FSGNJX-S-01", "2000",
FDIV and FSQRT passes when simulating in modelsim
2021-07-19 03:00:04 +00:00
"rv32f/I-FSQRT-S-01", "2000",
floating point infinite loop removed from imperas tests
2021-05-18 14:42:51 +00:00
"rv32f/I-FSW-01", "2000",
rv64f FLW passes imperas tests
2021-06-22 20:36:16 +00:00
"rv32f/I-FLW-01", "2110",
floating point infinite loop removed from imperas tests
2021-05-18 14:42:51 +00:00
"rv32f/I-FSUB-S-01", "2000"
};
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-30 19:25:07 +00:00
string tests64f[] = '{
rv64f FLW passes imperas tests
2021-06-22 20:36:16 +00:00
"rv64f/I-FLW-01", "2110",
all rv64f instructions except convert, divide, square root, and FLD pass
2021-06-21 00:24:09 +00:00
"rv64f/I-FMV-W-X-01", "2000",
"rv64f/I-FMV-X-W-01", "2000",
"rv64f/I-FSW-01", "2000",
floating point infinite loop removed from imperas tests
2021-05-18 14:42:51 +00:00
"rv64f/I-FCLASS-S-01", "2000",
all rv64f instructions except convert, divide, square root, and FLD pass
2021-06-21 00:24:09 +00:00
"rv64f/I-FADD-S-01", "2000",
Almost all convert instructions pass Imperas tests
2021-07-11 22:06:33 +00:00
"rv64f/I-FCVT-S-L-01", "2000",
"rv64f/I-FCVT-S-LU-01", "2000",
"rv64f/I-FCVT-S-W-01", "2000",
"rv64f/I-FCVT-S-WU-01", "2000",
"rv64f/I-FCVT-L-S-01", "2000",
"rv64f/I-FCVT-LU-S-01", "2000",
"rv64f/I-FCVT-W-S-01", "2000",
"rv64f/I-FCVT-WU-S-01", "2000",
fdivsqrt inegrated, but not completley working
2021-07-18 18:03:37 +00:00
"rv64f/I-FDIV-S-01", "2000",
floating point infinite loop removed from imperas tests
2021-05-18 14:42:51 +00:00
"rv64f/I-FEQ-S-01", "2000",
"rv64f/I-FLE-S-01", "2000",
"rv64f/I-FLT-S-01", "2000",
"rv64f/I-FMADD-S-01", "2000",
"rv64f/I-FMAX-S-01", "2000",
"rv64f/I-FMIN-S-01", "2000",
"rv64f/I-FMSUB-S-01", "2000",
"rv64f/I-FMUL-S-01", "2000",
"rv64f/I-FNMADD-S-01", "2000",
"rv64f/I-FNMSUB-S-01", "2000",
"rv64f/I-FSGNJ-S-01", "2000",
"rv64f/I-FSGNJN-S-01", "2000",
"rv64f/I-FSGNJX-S-01", "2000",
fdivsqrt inegrated, but not completley working
2021-07-18 18:03:37 +00:00
"rv64f/I-FSQRT-S-01", "2000",
floating point infinite loop removed from imperas tests
2021-05-18 14:42:51 +00:00
"rv64f/I-FSUB-S-01", "2000"
};
string tests64d[] = '{
Fixed writting MStatus FS bits
2021-07-13 17:20:30 +00:00
"rv64d/I-FSD-01", "2000",
"rv64d/I-FLD-01", "2420",
"rv64d/I-FMV-X-D-01", "2000",
"rv64d/I-FMV-D-X-01", "2000",
fixed lint warnings for fpu and lzd
2021-06-05 16:06:33 +00:00
// "rv64d/I-FDIV-D-01", "2000",
Almost all convert instructions pass Imperas tests
2021-07-11 22:06:33 +00:00
"rv64d/I-FCVT-D-L-01", "2000",
"rv64d/I-FCVT-D-LU-01", "2000",
fdivsqrt inegrated, but not completley working
2021-07-18 18:03:37 +00:00
"rv64d/I-FCVT-D-S-01", "2000",
Almost all convert instructions pass Imperas tests
2021-07-11 22:06:33 +00:00
"rv64d/I-FCVT-D-W-01", "2000",
"rv64d/I-FCVT-D-WU-01", "2000",
"rv64d/I-FCVT-L-D-01", "2000",
"rv64d/I-FCVT-LU-D-01", "2000",
fdivsqrt inegrated, but not completley working
2021-07-18 18:03:37 +00:00
"rv64d/I-FCVT-S-D-01", "2000",
Almost all convert instructions pass Imperas tests
2021-07-11 22:06:33 +00:00
"rv64d/I-FCVT-W-D-01", "2000",
fdivsqrt inegrated, but not completley working
2021-07-18 18:03:37 +00:00
"rv64d/I-FCVT-WU-D-01", "2000",
Double-precision FMA instructions
2021-06-04 18:00:11 +00:00
"rv64d/I-FNMADD-D-01", "2000",
"rv64d/I-FNMSUB-D-01", "2000",
"rv64d/I-FMSUB-D-01", "2000",
All compare instructions pass imperas tests
2021-05-27 19:23:28 +00:00
"rv64d/I-FMAX-D-01", "2000",
"rv64d/I-FMIN-D-01", "2000",
"rv64d/I-FLE-D-01", "2000",
"rv64d/I-FLT-D-01", "2000",
"rv64d/I-FEQ-D-01", "2000",
FADD and FSUB imperas tests pass
2021-05-26 16:33:33 +00:00
"rv64d/I-FADD-D-01", "2000",
classify unit created and passes imperas tests
2021-05-27 22:53:55 +00:00
"rv64d/I-FCLASS-D-01", "2000",
All compare instructions pass imperas tests
2021-05-27 19:23:28 +00:00
"rv64d/I-FMADD-D-01", "2000",
Double-precision FMA instructions
2021-06-04 18:00:11 +00:00
"rv64d/I-FMUL-D-01", "2000",
All compare instructions pass imperas tests
2021-05-27 19:23:28 +00:00
"rv64d/I-FSGNJ-D-01", "2000",
"rv64d/I-FSGNJN-D-01", "2000",
"rv64d/I-FSGNJX-D-01", "2000",
fdivsqrt inegrated, but not completley working
2021-07-18 18:03:37 +00:00
// "rv64d/I-FSQRT-D-01", "2000",
FADD and FSUB imperas tests pass
2021-05-26 16:33:33 +00:00
"rv64d/I-FSUB-D-01", "2000"
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-30 19:25:07 +00:00
};
Merge remote-tracking branch 'origin/main' into main Bring icache and MMU code together Conflicts: wally-pipelined/src/ifu/ifu.sv wally-pipelined/testbench/testbench-imperas.sv
2021-03-31 02:24:47 +00:00
WALLY-LRSC atomic test passing
2021-03-09 14:28:25 +00:00
string tests64a[] = '{
Started atomics
2021-07-18 01:11:41 +00:00
//"rv64a/WALLY-AMO", "2110",
merge testbench
2021-04-08 18:28:01 +00:00
"rv64a/WALLY-LRSC", "2110"
WALLY-LRSC atomic test passing
2021-03-09 14:28:25 +00:00
};
merge testbench
2021-04-08 18:28:01 +00:00
Added MUL
2021-02-16 03:27:35 +00:00
string tests64m[] = '{
merge testbench
2021-04-08 18:28:01 +00:00
"rv64m/I-MUL-01", "3000",
"rv64m/I-MULH-01", "3000",
"rv64m/I-MULHSU-01", "3000",
"rv64m/I-MULHU-01", "3000",
Mod Imperas Testbench for updated Div/Rem
2021-05-17 21:56:30 +00:00
"rv64m/I-MULW-01", "3000",
Mod for DIV/REM instruction and update to div.sv unit
2021-05-25 00:29:13 +00:00
"rv64m/I-DIV-01", "3000",
Mod Imperas Testbench for updated Div/Rem
2021-05-17 21:56:30 +00:00
"rv64m/I-DIVU-01", "3000",
Modify muldiv.sv to handle W instructions for 64-bits
2021-06-01 03:27:42 +00:00
"rv64m/I-DIVUW-01", "3000",
"rv64m/I-DIVW-01", "3000",
Mod for DIV/REM instruction and update to div.sv unit
2021-05-25 00:29:13 +00:00
"rv64m/I-REM-01", "3000",
Modify muldiv.sv to handle W instructions for 64-bits
2021-06-01 03:27:42 +00:00
"rv64m/I-REMU-01", "3000",
"rv64m/I-REMUW-01", "3000",
"rv64m/I-REMW-01", "3000"
Added MUL
2021-02-16 03:27:35 +00:00
};
merge testbench
2021-04-08 18:28:01 +00:00
Initial Checkin
2021-01-15 04:37:51 +00:00
string tests64ic[] = '{
merge testbench
2021-04-08 18:28:01 +00:00
"rv64ic/I-C-ADD-01", "3000",
"rv64ic/I-C-ADDI-01", "3000",
"rv64ic/I-C-ADDIW-01", "3000",
"rv64ic/I-C-ADDW-01", "3000",
"rv64ic/I-C-AND-01", "3000",
"rv64ic/I-C-ANDI-01", "3000",
"rv64ic/I-C-BEQZ-01", "3000",
"rv64ic/I-C-BNEZ-01", "3000",
"rv64ic/I-C-EBREAK-01", "2000",
"rv64ic/I-C-J-01", "3000",
"rv64ic/I-C-JALR-01", "4000",
"rv64ic/I-C-JR-01", "4000",
"rv64ic/I-C-LD-01", "3420",
"rv64ic/I-C-LDSP-01", "3420",
"rv64ic/I-C-LI-01", "3000",
"rv64ic/I-C-LUI-01", "2000",
"rv64ic/I-C-LW-01", "3110",
"rv64ic/I-C-LWSP-01", "3110",
"rv64ic/I-C-MV-01", "3000",
"rv64ic/I-C-NOP-01", "2000",
"rv64ic/I-C-OR-01", "3000",
"rv64ic/I-C-SD-01", "3000",
"rv64ic/I-C-SDSP-01", "3000",
"rv64ic/I-C-SLLI-01", "3000",
"rv64ic/I-C-SRAI-01", "3000",
"rv64ic/I-C-SRLI-01", "3000",
"rv64ic/I-C-SUB-01", "3000",
"rv64ic/I-C-SUBW-01", "3000",
"rv64ic/I-C-SW-01", "3000",
"rv64ic/I-C-SWSP-01", "3000",
"rv64ic/I-C-XOR-01", "3000"
Initial Checkin
2021-01-15 04:37:51 +00:00
};
merge testbench
2021-04-08 18:28:01 +00:00
string tests64iNOc[] = {
"rv64i/I-MISALIGN_JMP-01","2000"
Initial Checkin
2021-01-15 04:37:51 +00:00
};
added branch tests
2021-02-13 03:40:08 +00:00
merge testbench
2021-04-08 18:28:01 +00:00
string tests64i[] = '{
Commented out 100k tests to improve speed
2021-06-21 05:43:18 +00:00
//"rv64i/WALLY-PIPELINE-100K", "f7ff0",
Progress towards the test bench flush.
2021-07-12 19:22:13 +00:00
//"rv64i/WALLY-LOAD", "11bf0",
merge testbench
2021-04-08 18:28:01 +00:00
"rv64i/I-ADD-01", "3000",
"rv64i/I-ADDI-01", "3000",
"rv64i/I-ADDIW-01", "3000",
"rv64i/I-ADDW-01", "3000",
"rv64i/I-AND-01", "3000",
"rv64i/I-ANDI-01", "3000",
"rv64i/I-AUIPC-01", "3000",
"rv64i/I-BEQ-01", "4000",
"rv64i/I-BGE-01", "4000",
"rv64i/I-BGEU-01", "4000",
"rv64i/I-BLT-01", "4000",
"rv64i/I-BLTU-01", "4000",
"rv64i/I-BNE-01", "4000",
"rv64i/I-DELAY_SLOTS-01", "2000",
"rv64i/I-EBREAK-01", "2000",
"rv64i/I-ECALL-01", "2000",
"rv64i/I-ENDIANESS-01", "2010",
"rv64i/I-IO-01", "2050",
"rv64i/I-JAL-01", "3000",
"rv64i/I-JALR-01", "4000",
"rv64i/I-LB-01", "4020",
"rv64i/I-LBU-01", "4020",
"rv64i/I-LD-01", "4420",
"rv64i/I-LH-01", "4050",
"rv64i/I-LHU-01", "4050",
"rv64i/I-LUI-01", "2000",
"rv64i/I-LW-01", "4110",
"rv64i/I-LWU-01", "4110",
"rv64i/I-MISALIGN_LDST-01", "2010",
"rv64i/I-NOP-01", "2000",
"rv64i/I-OR-01", "3000",
"rv64i/I-ORI-01", "3000",
"rv64i/I-RF_size-01", "2000",
"rv64i/I-RF_width-01", "2000",
"rv64i/I-RF_x0-01", "2010",
"rv64i/I-SB-01", "4000",
"rv64i/I-SD-01", "4000",
"rv64i/I-SH-01", "4000",
"rv64i/I-SLL-01", "3000",
"rv64i/I-SLLI-01", "3000",
"rv64i/I-SLLIW-01", "3000",
"rv64i/I-SLLW-01", "3000",
"rv64i/I-SLT-01", "3000",
"rv64i/I-SLTI-01", "3000",
"rv64i/I-SLTIU-01", "3000",
"rv64i/I-SLTU-01", "3000",
"rv64i/I-SRA-01", "3000",
"rv64i/I-SRAI-01", "3000",
"rv64i/I-SRAIW-01", "3000",
"rv64i/I-SRAW-01", "3000",
"rv64i/I-SRL-01", "3000",
"rv64i/I-SRLI-01", "3000",
"rv64i/I-SRLIW-01", "3000",
"rv64i/I-SRLW-01", "3000",
"rv64i/I-SUB-01", "3000",
"rv64i/I-SUBW-01", "3000",
"rv64i/I-SW-01", "4000",
"rv64i/I-XOR-01", "3000",
"rv64i/I-XORI-01", "3000",
"rv64i/WALLY-ADD", "4000",
"rv64i/WALLY-SUB", "4000",
"rv64i/WALLY-ADDI", "3000",
"rv64i/WALLY-ANDI", "3000",
"rv64i/WALLY-ORI", "3000",
"rv64i/WALLY-XORI", "3000",
"rv64i/WALLY-SLTI", "3000",
"rv64i/WALLY-SLTIU", "3000",
"rv64i/WALLY-SLLI", "3000",
"rv64i/WALLY-SRLI", "3000",
"rv64i/WALLY-SRAI", "3000",
"rv64i/WALLY-JAL", "4000",
"rv64i/WALLY-JALR", "3000",
"rv64i/WALLY-STORE", "3000",
"rv64i/WALLY-ADDIW", "3000",
"rv64i/WALLY-SLLIW", "3000",
"rv64i/WALLY-SRLIW", "3000",
"rv64i/WALLY-SRAIW", "3000",
"rv64i/WALLY-ADDW", "4000",
"rv64i/WALLY-SUBW", "4000",
"rv64i/WALLY-SLLW", "3000",
"rv64i/WALLY-SRLW", "3000",
"rv64i/WALLY-SRAW", "3000",
"rv64i/WALLY-BEQ" ,"5000",
"rv64i/WALLY-BNE", "5000 ",
"rv64i/WALLY-BLTU", "5000 ",
"rv64i/WALLY-BLT", "5000",
"rv64i/WALLY-BGE", "5000 ",
"rv64i/WALLY-BGEU", "5000 ",
"rv64i/WALLY-CSRRW", "4000",
"rv64i/WALLY-CSRRS", "4000",
"rv64i/WALLY-CSRRC", "5000",
"rv64i/WALLY-CSRRWI", "4000",
"rv64i/WALLY-CSRRSI", "4000",
"rv64i/WALLY-CSRRCI", "4000"
Initial Checkin
2021-01-15 04:37:51 +00:00
};
merge testbench
2021-04-08 18:28:01 +00:00
Drafted rv32a tests
2021-03-12 05:06:23 +00:00
string tests32a[] = '{
Started atomics
2021-07-18 01:11:41 +00:00
//"rv64a/WALLY-AMO", "2110",
Fixed bug with rv32a/WALLY-LRSC test in imperas. Minor issue.
2021-07-18 02:02:24 +00:00
"rv32a/WALLY-LRSC", "2110"
Drafted rv32a tests
2021-03-12 05:06:23 +00:00
};
merge testbench
2021-04-08 18:28:01 +00:00
Added MUL
2021-02-16 03:27:35 +00:00
string tests32m[] = '{
merge testbench
2021-04-08 18:28:01 +00:00
"rv32m/I-MUL-01", "2000",
"rv32m/I-MULH-01", "2000",
"rv32m/I-MULHSU-01", "2000",
Updates to muldiv.sv for 32-bit div/rem
2021-06-01 19:31:07 +00:00
"rv32m/I-MULHU-01", "2000",
"rv32m/I-DIV-01", "2000",
"rv32m/I-DIVU-01", "2000",
"rv32m/I-REM-01", "2000",
"rv32m/I-REMU-01", "2000"
Added MUL
2021-02-16 03:27:35 +00:00
};
added branch tests
2021-02-13 03:40:08 +00:00
merge testbench
2021-04-08 18:28:01 +00:00
string tests32ic[] = '{
"rv32ic/I-C-ADD-01", "2000",
"rv32ic/I-C-ADDI-01", "2000",
"rv32ic/I-C-AND-01", "2000",
"rv32ic/I-C-ANDI-01", "2000",
"rv32ic/I-C-BEQZ-01", "2000",
"rv32ic/I-C-BNEZ-01", "2000",
"rv32ic/I-C-EBREAK-01", "2000",
"rv32ic/I-C-J-01", "2000",
"rv32ic/I-C-JALR-01", "3000",
"rv32ic/I-C-JR-01", "3000",
"rv32ic/I-C-LI-01", "2000",
"rv32ic/I-C-LUI-01", "2000",
"rv32ic/I-C-LW-01", "2110",
"rv32ic/I-C-LWSP-01", "2110",
"rv32ic/I-C-MV-01", "2000",
"rv32ic/I-C-NOP-01", "2000",
"rv32ic/I-C-OR-01", "2000",
"rv32ic/I-C-SLLI-01", "2000",
"rv32ic/I-C-SRAI-01", "2000",
"rv32ic/I-C-SRLI-01", "2000",
"rv32ic/I-C-SUB-01", "2000",
"rv32ic/I-C-SW-01", "2000",
"rv32ic/I-C-SWSP-01", "2000",
"rv32ic/I-C-XOR-01", "2000"
};
string tests32iNOc[] = {
"rv32i/I-MISALIGN_JMP-01","2000"
};
string tests32i[] = {
Commented out 100k tests to improve speed
2021-06-21 05:43:18 +00:00
//"rv32i/WALLY-PIPELINE-100K", "10a800",
merge testbench
2021-04-08 18:28:01 +00:00
"rv32i/I-ADD-01", "2000",
"rv32i/I-ADDI-01","2000",
"rv32i/I-AND-01","2000",
"rv32i/I-ANDI-01","2000",
"rv32i/I-AUIPC-01","2000",
"rv32i/I-BEQ-01","3000",
"rv32i/I-BGE-01","3000",
"rv32i/I-BGEU-01","3000",
"rv32i/I-BLT-01","3000",
"rv32i/I-BLTU-01","3000",
"rv32i/I-BNE-01","3000",
"rv32i/I-DELAY_SLOTS-01","2000",
"rv32i/I-EBREAK-01","2000",
"rv32i/I-ECALL-01","2000",
"rv32i/I-ENDIANESS-01","2010",
updated pipeline tests
2021-05-04 02:07:36 +00:00
"rv32i/I-IO-01","2030rv",
merge testbench
2021-04-08 18:28:01 +00:00
"rv32i/I-JAL-01","3000",
"rv32i/I-JALR-01","3000",
"rv32i/I-LB-01","3020",
"rv32i/I-LBU-01","3020",
"rv32i/I-LH-01","3050",
"rv32i/I-LHU-01","3050",
"rv32i/I-LUI-01","2000",
"rv32i/I-LW-01","3110",
"rv32i/I-MISALIGN_LDST-01","2010",
"rv32i/I-NOP-01","2000",
"rv32i/I-OR-01","2000",
"rv32i/I-ORI-01","2000",
"rv32i/I-RF_size-01","2000",
"rv32i/I-RF_width-01","2000",
"rv32i/I-RF_x0-01","2010",
"rv32i/I-SB-01","3000",
"rv32i/I-SH-01","3000",
"rv32i/I-SLL-01","2000",
"rv32i/I-SLLI-01","2000",
"rv32i/I-SLT-01","2000",
"rv32i/I-SLTI-01","2000",
"rv32i/I-SLTIU-01","2000",
"rv32i/I-SLTU-01","2000",
"rv32i/I-SRA-01","2000",
"rv32i/I-SRAI-01","2000",
"rv32i/I-SRL-01","2000",
"rv32i/I-SRLI-01","2000",
"rv32i/I-SUB-01","2000",
"rv32i/I-SW-01","3000",
"rv32i/I-XOR-01","2000",
"rv32i/I-XORI-01","2000",
"rv32i/WALLY-ADD", "3000",
"rv32i/WALLY-SUB", "3000",
"rv32i/WALLY-ADDI", "2000",
"rv32i/WALLY-ANDI", "2000",
"rv32i/WALLY-ORI", "2000",
"rv32i/WALLY-XORI", "2000",
"rv32i/WALLY-SLTI", "2000",
"rv32i/WALLY-SLTIU", "2000",
"rv32i/WALLY-SLLI", "2000",
"rv32i/WALLY-SRLI", "2000",
"rv32i/WALLY-SRAI", "2000",
"rv32i/WALLY-LOAD", "11c00",
"rv32i/WALLY-SUB", "3000",
"rv32i/WALLY-STORE", "2000",
"rv32i/WALLY-JAL", "3000",
"rv32i/WALLY-JALR", "2000",
"rv32i/WALLY-BEQ" ,"4000",
"rv32i/WALLY-BNE", "4000 ",
"rv32i/WALLY-BLTU", "4000 ",
"rv32i/WALLY-BLT", "4000",
"rv32i/WALLY-BGE", "4000 ",
"rv32i/WALLY-BGEU", "4000 ",
"rv32i/WALLY-CSRRW", "3000",
"rv32i/WALLY-CSRRS", "3000",
"rv32i/WALLY-CSRRC", "4000",
"rv32i/WALLY-CSRRWI", "3000",
"rv32i/WALLY-CSRRSI", "3000",
updated pipeline tests
2021-05-04 02:07:36 +00:00
"rv32i/WALLY-CSRRCI", "3000"
merge testbench
2021-04-08 18:28:01 +00:00
};
Added possibly working OSU test bench as a precursor to running a bp benchmark. Fixed a few bugs with the function radix.
2021-03-17 16:06:32 +00:00
string testsBP64[] = '{
Minor testbench updates to rv64icfd
2021-05-21 14:41:21 +00:00
"rv64BP/simple", "10000",
Now have global history working correctly.
2021-06-01 15:57:43 +00:00
"rv64BP/mmm", "1000000",
"rv64BP/linpack_bench", "1000000",
"rv64BP/sieve", "1000000",
Minor testbench updates to rv64icfd
2021-05-21 14:41:21 +00:00
"rv64BP/qsort", "1000000",
Now have global history working correctly.
2021-06-01 15:57:43 +00:00
"rv64BP/dhrystone", "1000000"
merge testbench
2021-04-08 18:28:01 +00:00
};
Add mcause tests to testbench
2021-03-30 21:17:59 +00:00
merge testbench
2021-04-08 18:28:01 +00:00
string tests64p[] = '{
partially complete MSTATUS test of sd, xs, fs, mie, mpp, mpie, sie, spie bitfields
2021-05-25 00:59:26 +00:00
"rv64p/WALLY-MSTATUS", "2000",
Use correct begin_signature for rv64p/MCAUSE and rv64p/SCAUSE
2021-05-04 05:04:12 +00:00
"rv64p/WALLY-MCAUSE", "3000",
"rv64p/WALLY-SCAUSE", "2000",
Add tests for scause, and improve tests for sepc. Also make improvements to privileged test generator run.sh file
2021-04-21 05:12:55 +00:00
"rv64p/WALLY-MEPC", "5000",
Add tests for sepc register
2021-04-21 03:50:53 +00:00
"rv64p/WALLY-SEPC", "4000",
Add tests for stval and mtval
2021-04-21 06:31:32 +00:00
"rv64p/WALLY-MTVAL", "6000",
"rv64p/WALLY-STVAL", "4000",
Add mtvec and stvec tests to testbench
2021-05-04 02:19:50 +00:00
"rv64p/WALLY-MTVEC", "2000",
"rv64p/WALLY-STVEC", "2000",
merge testbench
2021-04-08 18:28:01 +00:00
"rv64p/WALLY-MARCHID", "4000",
"rv64p/WALLY-MIMPID", "4000",
"rv64p/WALLY-MHARTID", "4000",
Added MIE tests to testbench
2021-05-04 06:22:01 +00:00
"rv64p/WALLY-MVENDORID", "4000",
Re-add medeleg tests to testbench
2021-05-04 18:42:20 +00:00
"rv64p/WALLY-MIE", "3000",
Added mip tests to testbench
2021-05-04 19:36:06 +00:00
"rv64p/WALLY-MEDELEG", "4000",
Forgot to add csr permission tests to testbench
2021-05-05 00:20:22 +00:00
"rv64p/WALLY-IP", "2000",
"rv64p/WALLY-CSR-PERMISSIONS-M", "5000",
"rv64p/WALLY-CSR-PERMISSIONS-S", "3000"
merge testbench
2021-04-08 18:28:01 +00:00
};
Cause an Illegal Instruction Exception when attempting to write readonly CSRs
2021-04-08 09:12:54 +00:00
Add 32 bit privileged tests
2021-04-15 20:55:39 +00:00
string tests32p[] = '{
partially complete MSTATUS test of sd, xs, fs, mie, mpp, mpie, sie, spie bitfields
2021-05-25 00:59:26 +00:00
"rv32p/WALLY-MSTATUS", "2000",
Fix 32 bit privileged tests!!!
2021-05-04 04:16:19 +00:00
"rv32p/WALLY-MCAUSE", "3000",
"rv32p/WALLY-SCAUSE", "2000",
"rv32p/WALLY-MEPC", "5000",
"rv32p/WALLY-SEPC", "4000",
"rv32p/WALLY-MTVAL", "5000",
"rv32p/WALLY-STVAL", "4000",
"rv32p/WALLY-MARCHID", "4000",
"rv32p/WALLY-MIMPID", "4000",
"rv32p/WALLY-MHARTID", "4000",
"rv32p/WALLY-MVENDORID", "4000",
"rv32p/WALLY-MTVEC", "2000",
Added MIE tests to testbench
2021-05-04 06:22:01 +00:00
"rv32p/WALLY-STVEC", "2000",
Re-add medeleg tests to testbench
2021-05-04 18:42:20 +00:00
"rv32p/WALLY-MIE", "3000",
Added mip tests to testbench
2021-05-04 19:36:06 +00:00
"rv32p/WALLY-MEDELEG", "4000",
Forgot to add csr permission tests to testbench
2021-05-05 00:20:22 +00:00
"rv32p/WALLY-IP", "3000",
"rv32p/WALLY-CSR-PERMISSIONS-M", "5000",
"rv32p/WALLY-CSR-PERMISSIONS-S", "3000"
Add 32 bit privileged tests
2021-04-15 20:55:39 +00:00
};
merge testbench
2021-04-08 18:28:01 +00:00
string tests64periph[] = '{
* GPIO comprehensive testing * MEPC more aware if M stage has actually committed * UART interrupt testing progress * UART added read IIR side effect of lowering THRE intr
2021-06-08 16:32:46 +00:00
"rv64i-periph/WALLY-PERIPH", "2000"
merge testbench
2021-04-08 18:28:01 +00:00
};
Cause an Illegal Instruction Exception when attempting to write readonly CSRs
2021-04-08 09:12:54 +00:00
merge testbench
2021-04-08 18:28:01 +00:00
string tests32periph[] = '{
working GPIO interrupt demo
2021-04-16 01:09:15 +00:00
"rv32i-periph/WALLY-PLIC", "2080"
merge testbench
2021-04-08 18:28:01 +00:00
};
Add mcause tests to testbench
2021-03-30 21:17:59 +00:00
Minor testbench updates to rv64icfd
2021-05-21 14:41:21 +00:00
string tests[];
Improve version of the function radix which does not cause the wave file rendering to slow down.
2021-03-11 23:12:21 +00:00
string ProgramAddrMapFile, ProgramLabelMapFile;
Connected AHB bus to Uncore
2021-01-30 04:43:48 +00:00
logic [`AHBW-1:0] HRDATAEXT;
logic HREADYEXT, HRESPEXT;
Added ahblite bus interface unit
2021-01-29 06:07:17 +00:00
logic [31:0] HADDR;
logic [`AHBW-1:0] HWDATA;
logic HWRITE;
logic [2:0] HSIZE;
logic [2:0] HBURST;
logic [3:0] HPROT;
logic [1:0] HTRANS;
logic HMASTLOCK;
Added HCLK and HRESETn
2021-01-30 05:56:12 +00:00
logic HCLK, HRESETn;
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-30 19:25:07 +00:00
logic [`XLEN-1:0] PCW;
Added F_SUPPORTED flag to disable floating point unit when not in MISA
2021-07-05 14:30:46 +00:00
Progress towards the test bench flush.
2021-07-12 19:22:13 +00:00
logic DCacheFlushDone, DCacheFlushStart;
hptw: minor cleanup
2021-07-17 17:40:12 +00:00
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-30 19:25:07 +00:00
flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.PCM, PCW);
flopenr #(32) InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW);
Fixed lint WIDTH errors
2021-06-10 00:58:20 +00:00
// check assertions for a legal configuration
riscvassertions riscvassertions();
Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
2021-07-04 05:19:38 +00:00
logging logging(clk, reset, dut.uncore.HADDR, dut.uncore.HTRANS);
Fixed lint WIDTH errors
2021-06-10 00:58:20 +00:00
Initial Checkin
2021-01-15 04:37:51 +00:00
// pick tests based on modes supported
Add mcause tests to testbench
2021-03-30 21:17:59 +00:00
initial begin
Replaced parameters with macros for XLEN, MISA, other configuration, and renamed wally-params.sv to wally-config.vh
2021-01-23 15:48:12 +00:00
if (`XLEN == 64) begin // RV64
Merge branch 'tests' into icache-almost-working
2021-04-26 02:25:36 +00:00
if (`TESTSBP) begin
Updated branch predictor tests/benchmarks.
2021-05-24 16:13:33 +00:00
tests = testsBP64;
// testsbp should not run the other tests. It starts at address 0 rather than
// 0x8000_0000, the next if must remain an else if.
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
2021-05-29 03:11:37 +00:00
end else if (TESTSPERIPH)
merge testbench
2021-04-08 18:28:01 +00:00
tests = tests64periph;
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
2021-05-29 03:11:37 +00:00
else if (TESTSPRIV)
tests = tests64p;
else begin
Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.
2021-07-15 16:56:35 +00:00
tests = {tests64p,tests64i, tests64periph};
Update virtual memory tests and move to separate folder
2021-03-31 02:18:29 +00:00
if (`C_SUPPORTED) tests = {tests, tests64ic};
else tests = {tests, tests64iNOc};
if (`M_SUPPORTED) tests = {tests, tests64m};
all rv64f instructions except convert, divide, square root, and FLD pass
2021-06-21 00:24:09 +00:00
if (`F_SUPPORTED) tests = {tests64f, tests};
FPU forwarding reworked pt.1
2021-06-24 22:39:18 +00:00
if (`D_SUPPORTED) tests = {tests64d, tests};
included virtual memory tests in testbench
2021-07-16 21:57:24 +00:00
if (`MEM_VIRTMEM) tests = {tests64mmu, tests};
Started atomics
2021-07-18 01:11:41 +00:00
if (`A_SUPPORTED) tests = {tests64a, tests};
Added possibly working OSU test bench as a precursor to running a bp benchmark. Fixed a few bugs with the function radix.
2021-03-17 16:06:32 +00:00
end
merge testbench
2021-04-08 18:28:01 +00:00
//tests = {tests64a, tests};
Initial Checkin
2021-01-15 04:37:51 +00:00
end else begin // RV32
Added possibly working OSU test bench as a precursor to running a bp benchmark. Fixed a few bugs with the function radix.
2021-03-17 16:06:32 +00:00
// *** add the 32 bit bp tests
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
2021-05-29 03:11:37 +00:00
if (TESTSPERIPH)
merge testbench
2021-04-08 18:28:01 +00:00
tests = tests32periph;
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
2021-05-29 03:11:37 +00:00
else if (TESTSPRIV)
tests = tests32p;
else begin
working testbench-imperas
2021-05-04 02:16:58 +00:00
tests = {tests32i, tests32p};//,tests32periph}; *** broken at the moment
merge testbench
2021-04-08 18:28:01 +00:00
if (`C_SUPPORTED % 2 == 1) tests = {tests, tests32ic};
else tests = {tests, tests32iNOc};
if (`M_SUPPORTED % 2 == 1) tests = {tests, tests32m};
Fixed writting MStatus FS bits
2021-07-13 17:20:30 +00:00
if (`F_SUPPORTED) tests = {tests32f, tests};
included virtual memory tests in testbench
2021-07-16 21:57:24 +00:00
if (`MEM_VIRTMEM) tests = {tests32mmu, tests};
Started atomics
2021-07-18 01:11:41 +00:00
if (`A_SUPPORTED) tests = {tests32a, tests};
end
Initial Checkin
2021-01-15 04:37:51 +00:00
end
Add mcause tests to testbench
2021-03-30 21:17:59 +00:00
end
Initial Checkin
2021-01-15 04:37:51 +00:00
string signame, memfilename;
Added GPIO
2021-01-15 05:25:56 +00:00
logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
Initial checkin of UART
2021-01-23 15:19:09 +00:00
logic UARTSin, UARTSout;
Added GPIO
2021-01-15 05:25:56 +00:00
Initial Checkin
2021-01-15 04:37:51 +00:00
// instantiate device to be tested
Changed to . notation for instantiation, cleaned up dmem
2021-01-19 01:16:53 +00:00
assign GPIOPinsIn = 0;
Repartitioned with Instruction Fetch Unit, Integer Execution Unit
2021-01-28 03:49:47 +00:00
assign UARTSin = 1;
Connected AHB bus to Uncore
2021-01-30 04:43:48 +00:00
assign HREADYEXT = 1;
assign HRESPEXT = 0;
assign HRDATAEXT = 0;
Added ahblite bus interface unit
2021-01-29 06:07:17 +00:00
wallypipelinedsoc dut(.*);
Initial Checkin
2021-01-15 04:37:51 +00:00
// Track names of instructions
Repartitioned datapath and controller into ieu
2021-01-27 11:40:26 +00:00
instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
Broken icache. Design is done. Time to debug.
2021-04-21 00:55:49 +00:00
dut.hart.ifu.icache.controller.FinalInstrRawF,
rv64i linear control flow now working
2021-03-24 20:56:44 +00:00
dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
Data memory bus integration
2021-02-08 04:21:55 +00:00
dut.hart.ifu.InstrM, dut.hart.ifu.InstrW,
Debugging instruction fetch
2021-02-09 16:02:17 +00:00
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
Initial Checkin
2021-01-15 04:37:51 +00:00
Moving data memory to uncore
2021-01-29 20:37:51 +00:00
// initialize tests
allow all size memory access in CLINT; added underscore to peripheral address symbols
2021-06-18 12:05:50 +00:00
localparam integer MemStartAddr = `TIM_BASE>>(1+`XLEN/32);
localparam integer MemEndAddr = (`TIM_RANGE+`TIM_BASE)>>1+(`XLEN/32);
Switch to use RV64IC for the benchmarks. Still not working correctly with the icache. instr addr correct got
2021-04-08 00:12:43 +00:00
Initial Checkin
2021-01-15 04:37:51 +00:00
initial
begin
test = 0;
totalerrors = 0;
testadr = 0;
// fill memory with defined values to reduce Xs in simulation
Switch to use RV64IC for the benchmarks. Still not working correctly with the icache. instr addr correct got
2021-04-08 00:12:43 +00:00
// Quick note the memory will need to be initialized. The C library does not
// guarantee the initialized reads. For example a strcmp can read 6 byte
// strings, but uses a load double to read them in. If the last 2 bytes are
// not initialized the compare results in an 'x' which propagates through
// the design.
Replaced parameters with macros for XLEN, MISA, other configuration, and renamed wally-params.sv to wally-config.vh
2021-01-23 15:48:12 +00:00
if (`XLEN == 32) meminit = 32'hFEDC0123;
Initial Checkin
2021-01-15 04:37:51 +00:00
else meminit = 64'hFEDCBA9876543210;
merge cleanup; mem init is broken
2021-04-26 12:00:17 +00:00
// *** broken because DTIM also drives RAM
Updated branch predictor tests/benchmarks.
2021-05-24 16:13:33 +00:00
if (`TESTSBP) begin
for (i=MemStartAddr; i<MemEndAddr; i = i+1) begin
dut.uncore.dtim.RAM[i] = meminit;
end
end
Initial Checkin
2021-01-15 04:37:51 +00:00
// read test vectors into memory
Added test configurations
2021-01-25 16:28:43 +00:00
memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
Moving data memory to uncore
2021-01-29 20:37:51 +00:00
$readmemh(memfilename, dut.uncore.dtim.RAM);
Improve version of the function radix which does not cause the wave file rendering to slow down.
2021-03-11 23:12:21 +00:00
ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"};
ProgramLabelMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.lab"};
WALLY-LRSC atomic test passing
2021-03-09 14:28:25 +00:00
$display("Read memfile %s", memfilename);
Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary. About 149307ns of simulation run.
2021-02-19 03:32:15 +00:00
reset = 1; # 42; reset = 0;
Initial Checkin
2021-01-15 04:37:51 +00:00
end
// generate clock to sequence tests
always
begin
clk = 1; # 5; clk = 0; # 5;
end
// check results
always @(negedge clk)
begin
Got the shadow ram cache flush working.
2021-07-13 15:03:47 +00:00
/* -----\/----- EXCLUDED -----\/-----
Moved privileged unit from datapath to hart
2021-01-27 12:46:52 +00:00
if (dut.hart.priv.EcallFaultM &&
Team work on solving the dcache data inconsistency problem.
2021-07-13 04:46:32 +00:00
(dut.hart.ieu.dp.regf.rf[3] == 1 ||
(dut.hart.ieu.dp.regf.we3 &&
dut.hart.ieu.dp.regf.a3 == 3 &&
dut.hart.ieu.dp.regf.wd3 == 1))) begin
Got the shadow ram cache flush working.
2021-07-13 15:03:47 +00:00
-----/\----- EXCLUDED -----/\----- */
if (DCacheFlushDone) begin
Removed more unused signals from ahblite
2021-07-17 06:21:54 +00:00
//$display("Code ended with ecall with gp = 1");
Progress towards the test bench flush.
2021-07-12 19:22:13 +00:00
Team work on solving the dcache data inconsistency problem.
2021-07-13 04:46:32 +00:00
#600; // give time for instructions in pipeline to finish
Initial Checkin
2021-01-15 04:37:51 +00:00
// clear signature to prevent contamination from previous tests
updated pipeline tests
2021-05-04 02:07:36 +00:00
for(i=0; i<SIGNATURESIZE; i=i+1) begin
Initial Checkin
2021-01-15 04:37:51 +00:00
sig32[i] = 'bx;
end
// read signature, reformat in 64 bits if necessary
Added test configurations
2021-01-25 16:28:43 +00:00
signame = {"../../imperas-riscv-tests/work/", tests[test], ".signature.output"};
Initial Checkin
2021-01-15 04:37:51 +00:00
$readmemh(signame, sig32);
i = 0;
updated pipeline tests
2021-05-04 02:07:36 +00:00
while (i < SIGNATURESIZE) begin
Replaced parameters with macros for XLEN, MISA, other configuration, and renamed wally-params.sv to wally-config.vh
2021-01-23 15:48:12 +00:00
if (`XLEN == 32) begin
Initial Checkin
2021-01-15 04:37:51 +00:00
signature[i] = sig32[i];
i = i+1;
end else begin
signature[i/2] = {sig32[i+1], sig32[i]};
i = i + 2;
end
Fixed testbench to produce error when signature.output doesn't exist
2021-05-04 05:19:44 +00:00
if (sig32[i-1] === 'bx) begin
if (i == 1) begin
i = SIGNATURESIZE+1; // flag empty file
$display(" Error: empty test file");
end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
end
Initial Checkin
2021-01-15 04:37:51 +00:00
end
// Check errors
Fixed testbench to produce error when signature.output doesn't exist
2021-05-04 05:19:44 +00:00
errors = (i == SIGNATURESIZE+1); // error if file is empty
Initial Checkin
2021-01-15 04:37:51 +00:00
i = 0;
Added F_SUPPORTED flag to disable floating point unit when not in MISA
2021-07-05 14:30:46 +00:00
testadr = (`TIM_BASE+tests[test+1].atohex())/(`XLEN/8);
Initial Checkin
2021-01-15 04:37:51 +00:00
/* verilator lint_off INFINITELOOP */
while (signature[i] !== 'bx) begin
//$display("signature[%h] = %h", i, signature[i]);
Team work on solving the dcache data inconsistency problem.
2021-07-13 04:46:32 +00:00
if (signature[i] !== dut.uncore.dtim.RAM[testadr+i] &&
(signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
Initial Checkin
2021-01-15 04:37:51 +00:00
if (signature[i+4] !== 'bx || signature[i] !== 32'hFFFFFFFF) begin
// report errors unless they are garbage at the end of the sim
// kind of hacky test for garbage right now
errors = errors+1;
Started atomics
2021-07-18 01:11:41 +00:00
$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (TIM) = %h, signature = %h",
tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.uncore.dtim.RAM[testadr+i], signature[i]);
FMV.D.X imperas test passes
2021-05-21 02:17:59 +00:00
$stop;//***debug
Initial Checkin
2021-01-15 04:37:51 +00:00
end
end
i = i + 1;
end
/* verilator lint_on INFINITELOOP */
Added F_SUPPORTED flag to disable floating point unit when not in MISA
2021-07-05 14:30:46 +00:00
if (errors == 0) begin
$display("%s succeeded. Brilliant!!!", tests[test]);
end
Initial Checkin
2021-01-15 04:37:51 +00:00
else begin
$display("%s failed with %d errors. :(", tests[test], errors);
totalerrors = totalerrors+1;
end
test = test + 2;
if (test == tests.size()) begin
if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
else $display("FAIL: %d test programs had errors", totalerrors);
$stop;
end
else begin
Added test configurations
2021-01-25 16:28:43 +00:00
memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
Moving data memory to uncore
2021-01-29 20:37:51 +00:00
$readmemh(memfilename, dut.uncore.dtim.RAM);
Initial Checkin
2021-01-15 04:37:51 +00:00
$display("Read memfile %s", memfilename);
Improve version of the function radix which does not cause the wave file rendering to slow down.
2021-03-11 23:12:21 +00:00
ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"};
ProgramLabelMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.lab"};
Initial Checkin
2021-01-15 04:37:51 +00:00
reset = 1; # 17; reset = 0;
end
end
Updating the test bench to include a function radix. Not done.
2021-02-27 01:43:40 +00:00
end // always @ (negedge clk)
Finally I think I have the function radix mapping across all applications correctly. I still need to clean up the code a bit so it is easier to understand.
2021-03-10 17:00:51 +00:00
// track the current function or global label
Updated the function radix to have a new name FunctionName and it now pervents false transisions from the current function name when the PCD is flushed.
2021-03-24 18:03:43 +00:00
if (DEBUG == 1) begin : FunctionName
FunctionName FunctionName(.reset(reset),
.clk(clk),
.ProgramAddrMapFile(ProgramAddrMapFile),
.ProgramLabelMapFile(ProgramLabelMapFile));
Improve version of the function radix which does not cause the wave file rendering to slow down.
2021-03-11 23:12:21 +00:00
end
Converted branch predictor preloads to use system verilog rather than modelsim's load command.
2021-03-15 17:39:44 +00:00
Progress towards the test bench flush.
2021-07-12 19:22:13 +00:00
assign DCacheFlushStart = dut.hart.priv.EcallFaultM &&
(dut.hart.ieu.dp.regf.rf[3] == 1 ||
(dut.hart.ieu.dp.regf.we3 &&
dut.hart.ieu.dp.regf.a3 == 3 &&
dut.hart.ieu.dp.regf.wd3 == 1));
DCacheFlushFSM DCacheFlushFSM(.clk(clk),
.reset(reset),
.start(DCacheFlushStart),
.done(DCacheFlushDone));
Added the ability to exclude branch predictor.
2021-04-26 19:27:42 +00:00
generate
// initialize the branch predictor
if (`BPRED_ENABLED == 1) begin : bpred
initial begin
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);
end
end
endgenerate
Added debug option to disable the function radix if not needed. Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
2021-03-10 21:17:02 +00:00
Initial Checkin
2021-01-15 04:37:51 +00:00
endmodule
Fixed lint WIDTH errors
2021-06-10 00:58:20 +00:00
module riscvassertions();
// Legal number of PMP entries are 0, 16, or 64
initial begin
Parameterized I$/D$ configurations and added sanity check assertions in testbench
2021-07-20 12:57:13 +00:00
assert (`PMP_ENTRIES == 0 || `PMP_ENTRIES==16 || `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
2021-07-04 05:19:38 +00:00
assert (`F_SUPPORTED || ~`D_SUPPORTED) else $error("Can't support double without supporting float");
hptw: factored pregen
2021-07-17 15:11:10 +00:00
assert (`XLEN == 64 || ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32");
Parameterized I$/D$ configurations and added sanity check assertions in testbench
2021-07-20 12:57:13 +00:00
assert (`DCACHE_WAYSIZEINBYTES <= 4096 || `MEM_DCACHE == 0 || `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`DCACHE_BLOCKLENINBITS >= 128 || `MEM_DCACHE == 0) else $error("DCACHE_BLOCKLENINBITS must be at least 128 when caches are enabled");
assert (`DCACHE_BLOCKLENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_BLOCKLENINBITS must be smaller than way size");
assert (`ICACHE_WAYSIZEINBYTES <= 4096 || `MEM_ICACHE == 0 || `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
assert (`ICACHE_BLOCKLENINBITS >= 32 || `MEM_ICACHE == 0) else $error("ICACHE_BLOCKLENINBITS must be at least 32 when caches are enabled");
assert (`ICACHE_BLOCKLENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_BLOCKLENINBITS must be smaller than way size");
assert (2**$clog2(`DCACHE_BLOCKLENINBITS) == `DCACHE_BLOCKLENINBITS) else $error("DCACHE_BLOCKLENINBITS must be a power of 2");
assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
assert (2**$clog2(`ICACHE_BLOCKLENINBITS) == `ICACHE_BLOCKLENINBITS) else $error("ICACHE_BLOCKLENINBITS must be a power of 2");
assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
assert (`ICACHE_NUMWAYS == 1 || `MEM_ICACHE == 0) else $error("Multiple Instruction Cache ways not yet implemented");
assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES) else $error("ITLB_ENTRIES must be a power of 2");
assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES) else $error("DTLB_ENTRIES must be a power of 2");
Fixed lint WIDTH errors
2021-06-10 00:58:20 +00:00
end
endmodule
Parameterized I$/D$ configurations and added sanity check assertions in testbench
2021-07-20 12:57:13 +00:00
Initial Checkin
2021-01-15 04:37:51 +00:00
/* verilator lint_on STMTDLY */
/* verilator lint_on WIDTH */
Replaced parameters with macros for XLEN, MISA, other configuration, and renamed wally-params.sv to wally-config.vh
2021-01-23 15:48:12 +00:00
module instrTrackerTB(
Initial Checkin
2021-01-15 04:37:51 +00:00
input logic clk, reset, FlushE,
Debugging instruction fetch
2021-02-09 16:02:17 +00:00
input logic [31:0] InstrF, InstrD,
Initial Checkin
2021-01-15 04:37:51 +00:00
input logic [31:0] InstrE, InstrM,
Data memory bus integration
2021-02-08 04:21:55 +00:00
input logic [31:0] InstrW,
// output logic [31:0] InstrW,
Debugging instruction fetch
2021-02-09 16:02:17 +00:00
output string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
Initial Checkin
2021-01-15 04:37:51 +00:00
// stage Instr to Writeback for visualization
Data memory bus integration
2021-02-08 04:21:55 +00:00
// flopr #(32) InstrWReg(clk, reset, InstrM, InstrW);
Initial Checkin
2021-01-15 04:37:51 +00:00
Debugging instruction fetch
2021-02-09 16:02:17 +00:00
instrNameDecTB fdec(InstrF, InstrFName);
Initial Checkin
2021-01-15 04:37:51 +00:00
instrNameDecTB ddec(InstrD, InstrDName);
instrNameDecTB edec(InstrE, InstrEName);
instrNameDecTB mdec(InstrM, InstrMName);
instrNameDecTB wdec(InstrW, InstrWName);
endmodule
// decode the instruction name, to help the test bench
module instrNameDecTB(
input logic [31:0] instr,
output string name);
logic [6:0] op;
logic [2:0] funct3;
logic [6:0] funct7;
logic [11:0] imm;
floating point infinite loop removed from imperas tests
2021-05-18 14:42:51 +00:00
logic [4:0] rs2;
Initial Checkin
2021-01-15 04:37:51 +00:00
assign op = instr[6:0];
assign funct3 = instr[14:12];
assign funct7 = instr[31:25];
assign imm = instr[31:20];
floating point infinite loop removed from imperas tests
2021-05-18 14:42:51 +00:00
assign rs2 = instr[24:20];
Initial Checkin
2021-01-15 04:37:51 +00:00
// it would be nice to add the operands to the name
// create another variable called decoded
always_comb
casez({op, funct3})
10'b0000000_000: name = "BAD";
10'b0000011_000: name = "LB";
10'b0000011_001: name = "LH";
10'b0000011_010: name = "LW";
10'b0000011_011: name = "LD";
10'b0000011_100: name = "LBU";
10'b0000011_101: name = "LHU";
10'b0000011_110: name = "LWU";
10'b0010011_000: if (instr[31:15] == 0 && instr[11:7] ==0) name = "NOP/FLUSH";
else name = "ADDI";
10'b0010011_001: if (funct7[6:1] == 6'b000000) name = "SLLI";
else name = "ILLEGAL";
10'b0010011_010: name = "SLTI";
10'b0010011_011: name = "SLTIU";
10'b0010011_100: name = "XORI";
10'b0010011_101: if (funct7[6:1] == 6'b000000) name = "SRLI";
else if (funct7[6:1] == 6'b010000) name = "SRAI";
else name = "ILLEGAL";
10'b0010011_110: name = "ORI";
10'b0010011_111: name = "ANDI";
10'b0010111_???: name = "AUIPC";
10'b0100011_000: name = "SB";
10'b0100011_001: name = "SH";
10'b0100011_010: name = "SW";
10'b0100011_011: name = "SD";
10'b0011011_000: name = "ADDIW";
10'b0011011_001: name = "SLLIW";
10'b0011011_101: if (funct7 == 7'b0000000) name = "SRLIW";
else if (funct7 == 7'b0100000) name = "SRAIW";
else name = "ILLEGAL";
10'b0111011_000: if (funct7 == 7'b0000000) name = "ADDW";
else if (funct7 == 7'b0100000) name = "SUBW";
Added MUL
2021-02-16 03:27:35 +00:00
else if (funct7 == 7'b0000001) name = "MULW";
else name = "ILLEGAL";
10'b0111011_001: if (funct7 == 7'b0000000) name = "SLLW";
else if (funct7 == 7'b0000001) name = "DIVW";
Initial Checkin
2021-01-15 04:37:51 +00:00
else name = "ILLEGAL";
10'b0111011_101: if (funct7 == 7'b0000000) name = "SRLW";
else if (funct7 == 7'b0100000) name = "SRAW";
Added MUL
2021-02-16 03:27:35 +00:00
else if (funct7 == 7'b0000001) name = "DIVUW";
else name = "ILLEGAL";
10'b0111011_110: if (funct7 == 7'b0000001) name = "REMW";
else name = "ILLEGAL";
10'b0111011_111: if (funct7 == 7'b0000001) name = "REMUW";
Initial Checkin
2021-01-15 04:37:51 +00:00
else name = "ILLEGAL";
10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD";
else if (funct7 == 7'b0000001) name = "MUL";
else if (funct7 == 7'b0100000) name = "SUB";
else name = "ILLEGAL";
10'b0110011_001: if (funct7 == 7'b0000000) name = "SLL";
else if (funct7 == 7'b0000001) name = "MULH";
else name = "ILLEGAL";
10'b0110011_010: if (funct7 == 7'b0000000) name = "SLT";
else if (funct7 == 7'b0000001) name = "MULHSU";
else name = "ILLEGAL";
10'b0110011_011: if (funct7 == 7'b0000000) name = "SLTU";
Multiply instructions working
2021-02-17 20:29:20 +00:00
else if (funct7 == 7'b0000001) name = "MULHU";
Initial Checkin
2021-01-15 04:37:51 +00:00
else name = "ILLEGAL";
10'b0110011_100: if (funct7 == 7'b0000000) name = "XOR";
Multiply instructions working
2021-02-17 20:29:20 +00:00
else if (funct7 == 7'b0000001) name = "DIV";
Initial Checkin
2021-01-15 04:37:51 +00:00
else name = "ILLEGAL";
10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL";
else if (funct7 == 7'b0000001) name = "DIVU";
else if (funct7 == 7'b0100000) name = "SRA";
else name = "ILLEGAL";
10'b0110011_110: if (funct7 == 7'b0000000) name = "OR";
else if (funct7 == 7'b0000001) name = "REM";
else name = "ILLEGAL";
10'b0110011_111: if (funct7 == 7'b0000000) name = "AND";
else if (funct7 == 7'b0000001) name = "REMU";
else name = "ILLEGAL";
10'b0110111_???: name = "LUI";
10'b1100011_000: name = "BEQ";
10'b1100011_001: name = "BNE";
10'b1100011_100: name = "BLT";
10'b1100011_101: name = "BGE";
10'b1100011_110: name = "BLTU";
10'b1100011_111: name = "BGEU";
10'b1100111_000: name = "JALR";
10'b1101111_???: name = "JAL";
10'b1110011_000: if (imm == 0) name = "ECALL";
else if (imm == 1) name = "EBREAK";
else if (imm == 2) name = "URET";
else if (imm == 258) name = "SRET";
else if (imm == 770) name = "MRET";
else name = "ILLEGAL";
10'b1110011_001: name = "CSRRW";
10'b1110011_010: name = "CSRRS";
10'b1110011_011: name = "CSRRC";
10'b1110011_101: name = "CSRRWI";
10'b1110011_110: name = "CSRRSI";
10'b1110011_111: name = "CSRRCI";
WALLY-LRSC atomic test passing
2021-03-09 14:28:25 +00:00
10'b0101111_010: if (funct7[6:2] == 5'b00010) name = "LR.W";
else if (funct7[6:2] == 5'b00011) name = "SC.W";
else if (funct7[6:2] == 5'b00001) name = "AMOSWAP.W";
else if (funct7[6:2] == 5'b00000) name = "AMOADD.W";
else if (funct7[6:2] == 5'b00100) name = "AMOAXOR.W";
else if (funct7[6:2] == 5'b01100) name = "AMOAND.W";
else if (funct7[6:2] == 5'b01000) name = "AMOOR.W";
else if (funct7[6:2] == 5'b10000) name = "AMOMIN.W";
else if (funct7[6:2] == 5'b10100) name = "AMOMAX.W";
else if (funct7[6:2] == 5'b11000) name = "AMOMINU.W";
else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.W";
else name = "ILLEGAL";
10'b0101111_011: if (funct7[6:2] == 5'b00010) name = "LR.D";
else if (funct7[6:2] == 5'b00011) name = "SC.D";
else if (funct7[6:2] == 5'b00001) name = "AMOSWAP.D";
else if (funct7[6:2] == 5'b00000) name = "AMOADD.D";
else if (funct7[6:2] == 5'b00100) name = "AMOAXOR.D";
else if (funct7[6:2] == 5'b01100) name = "AMOAND.D";
else if (funct7[6:2] == 5'b01000) name = "AMOOR.D";
else if (funct7[6:2] == 5'b10000) name = "AMOMIN.D";
else if (funct7[6:2] == 5'b10100) name = "AMOMAX.D";
else if (funct7[6:2] == 5'b11000) name = "AMOMINU.D";
else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.D";
else name = "ILLEGAL";
Initial Checkin
2021-01-15 04:37:51 +00:00
10'b0001111_???: name = "FENCE";
floating point infinite loop removed from imperas tests
2021-05-18 14:42:51 +00:00
10'b1000011_???: name = "FMADD";
10'b1000111_???: name = "FMSUB";
10'b1001011_???: name = "FNMSUB";
10'b1001111_???: name = "FNMADD";
10'b1010011_000: if (funct7[6:2] == 5'b00000) name = "FADD";
else if (funct7[6:2] == 5'b00001) name = "FSUB";
else if (funct7[6:2] == 5'b00010) name = "FMUL";
else if (funct7[6:2] == 5'b00011) name = "FDIV";
else if (funct7[6:2] == 5'b01011) name = "FSQRT";
else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
Almost all convert instructions pass Imperas tests
2021-07-11 22:06:33 +00:00
else if (funct7 == 7'b1100000 && rs2 == 5'b00010) name = "FCVT.L.S";
else if (funct7 == 7'b1100000 && rs2 == 5'b00011) name = "FCVT.LU.S";
floating point infinite loop removed from imperas tests
2021-05-18 14:42:51 +00:00
else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
Almost all convert instructions pass Imperas tests
2021-07-11 22:06:33 +00:00
else if (funct7 == 7'b1101000 && rs2 == 5'b00010) name = "FCVT.S.L";
else if (funct7 == 7'b1101000 && rs2 == 5'b00011) name = "FCVT.S.LU";
else if (funct7 == 7'b1100001 && rs2 == 5'b00000) name = "FCVT.W.D";
else if (funct7 == 7'b1100001 && rs2 == 5'b00001) name = "FCVT.WU.D";
else if (funct7 == 7'b1100001 && rs2 == 5'b00010) name = "FCVT.L.D";
else if (funct7 == 7'b1100001 && rs2 == 5'b00011) name = "FCVT.LU.D";
else if (funct7 == 7'b1101001 && rs2 == 5'b00000) name = "FCVT.D.W";
else if (funct7 == 7'b1101001 && rs2 == 5'b00001) name = "FCVT.D.WU";
else if (funct7 == 7'b1101001 && rs2 == 5'b00010) name = "FCVT.D.L";
else if (funct7 == 7'b1101001 && rs2 == 5'b00011) name = "FCVT.D.LU";
else if (funct7 == 7'b0100000 && rs2 == 5'b00001) name = "FCVT.S.D";
else if (funct7 == 7'b0100001 && rs2 == 5'b00000) name = "FCVT.D.S";
floating point infinite loop removed from imperas tests
2021-05-18 14:42:51 +00:00
else if (funct7 == 7'b1110000 && rs2 == 5'b00000) name = "FMV.X.W";
else if (funct7 == 7'b1111000 && rs2 == 5'b00000) name = "FMV.W.X";
FMV.X.D imperas test passes
2021-05-24 18:44:30 +00:00
else if (funct7 == 7'b1110001 && rs2 == 5'b00000) name = "FMV.X.D"; // DOUBLE
else if (funct7 == 7'b1111001 && rs2 == 5'b00000) name = "FMV.D.X"; // DOUBLE
floating point infinite loop removed from imperas tests
2021-05-18 14:42:51 +00:00
else if (funct7[6:2] == 5'b00100) name = "FSGNJ";
else if (funct7[6:2] == 5'b00101) name = "FMIN";
else if (funct7[6:2] == 5'b10100) name = "FLE";
else name = "ILLEGAL";
10'b1010011_001: if (funct7[6:2] == 5'b00000) name = "FADD";
else if (funct7[6:2] == 5'b00001) name = "FSUB";
else if (funct7[6:2] == 5'b00010) name = "FMUL";
else if (funct7[6:2] == 5'b00011) name = "FDIV";
else if (funct7[6:2] == 5'b01011) name = "FSQRT";
else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
Almost all convert instructions pass Imperas tests
2021-07-11 22:06:33 +00:00
else if (funct7 == 7'b1100000 && rs2 == 5'b00010) name = "FCVT.L.S";
else if (funct7 == 7'b1100000 && rs2 == 5'b00011) name = "FCVT.LU.S";
floating point infinite loop removed from imperas tests
2021-05-18 14:42:51 +00:00
else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
Almost all convert instructions pass Imperas tests
2021-07-11 22:06:33 +00:00
else if (funct7 == 7'b1101000 && rs2 == 5'b00010) name = "FCVT.S.L";
else if (funct7 == 7'b1101000 && rs2 == 5'b00011) name = "FCVT.S.LU";
else if (funct7 == 7'b1100001 && rs2 == 5'b00000) name = "FCVT.W.D";
else if (funct7 == 7'b1100001 && rs2 == 5'b00001) name = "FCVT.WU.D";
else if (funct7 == 7'b1100001 && rs2 == 5'b00010) name = "FCVT.L.D";
else if (funct7 == 7'b1100001 && rs2 == 5'b00011) name = "FCVT.LU.D";
else if (funct7 == 7'b1101001 && rs2 == 5'b00000) name = "FCVT.D.W";
else if (funct7 == 7'b1101001 && rs2 == 5'b00001) name = "FCVT.D.WU";
else if (funct7 == 7'b1101001 && rs2 == 5'b00010) name = "FCVT.D.L";
else if (funct7 == 7'b1101001 && rs2 == 5'b00011) name = "FCVT.D.LU";
else if (funct7 == 7'b0100000 && rs2 == 5'b00001) name = "FCVT.S.D";
else if (funct7 == 7'b0100001 && rs2 == 5'b00000) name = "FCVT.D.S";
floating point infinite loop removed from imperas tests
2021-05-18 14:42:51 +00:00
else if (funct7[6:2] == 5'b00100) name = "FSGNJN";
else if (funct7[6:2] == 5'b00101) name = "FMAX";
else if (funct7[6:2] == 5'b10100) name = "FLT";
else if (funct7[6:2] == 5'b11100) name = "FCLASS";
else name = "ILLEGAL";
Almost all convert instructions pass Imperas tests
2021-07-11 22:06:33 +00:00
10'b1010011_010: if (funct7[6:2] == 5'b00000) name = "FADD";
floating point infinite loop removed from imperas tests
2021-05-18 14:42:51 +00:00
else if (funct7[6:2] == 5'b00001) name = "FSUB";
else if (funct7[6:2] == 5'b00010) name = "FMUL";
else if (funct7[6:2] == 5'b00011) name = "FDIV";
else if (funct7[6:2] == 5'b01011) name = "FSQRT";
else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
Almost all convert instructions pass Imperas tests
2021-07-11 22:06:33 +00:00
else if (funct7 == 7'b1100000 && rs2 == 5'b00010) name = "FCVT.L.S";
else if (funct7 == 7'b1100000 && rs2 == 5'b00011) name = "FCVT.LU.S";
floating point infinite loop removed from imperas tests
2021-05-18 14:42:51 +00:00
else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
Almost all convert instructions pass Imperas tests
2021-07-11 22:06:33 +00:00
else if (funct7 == 7'b1101000 && rs2 == 5'b00010) name = "FCVT.S.L";
else if (funct7 == 7'b1101000 && rs2 == 5'b00011) name = "FCVT.S.LU";
else if (funct7 == 7'b1100001 && rs2 == 5'b00000) name = "FCVT.W.D";
else if (funct7 == 7'b1100001 && rs2 == 5'b00001) name = "FCVT.WU.D";
else if (funct7 == 7'b1100001 && rs2 == 5'b00010) name = "FCVT.L.D";
else if (funct7 == 7'b1100001 && rs2 == 5'b00011) name = "FCVT.LU.D";
else if (funct7 == 7'b1101001 && rs2 == 5'b00000) name = "FCVT.D.W";
else if (funct7 == 7'b1101001 && rs2 == 5'b00001) name = "FCVT.D.WU";
else if (funct7 == 7'b1101001 && rs2 == 5'b00010) name = "FCVT.D.L";
else if (funct7 == 7'b1101001 && rs2 == 5'b00011) name = "FCVT.D.LU";
else if (funct7 == 7'b0100000 && rs2 == 5'b00001) name = "FCVT.S.D";
else if (funct7 == 7'b0100001 && rs2 == 5'b00000) name = "FCVT.D.S";
floating point infinite loop removed from imperas tests
2021-05-18 14:42:51 +00:00
else if (funct7[6:2] == 5'b00100) name = "FSGNJX";
else if (funct7[6:2] == 5'b10100) name = "FEQ";
else name = "ILLEGAL";
10'b1010011_???: if (funct7[6:2] == 5'b00000) name = "FADD";
else if (funct7[6:2] == 5'b00001) name = "FSUB";
else if (funct7[6:2] == 5'b00010) name = "FMUL";
else if (funct7[6:2] == 5'b00011) name = "FDIV";
else if (funct7[6:2] == 5'b01011) name = "FSQRT";
else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
Almost all convert instructions pass Imperas tests
2021-07-11 22:06:33 +00:00
else if (funct7 == 7'b1100000 && rs2 == 5'b00010) name = "FCVT.L.S";
else if (funct7 == 7'b1100000 && rs2 == 5'b00011) name = "FCVT.LU.S";
floating point infinite loop removed from imperas tests
2021-05-18 14:42:51 +00:00
else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
Almost all convert instructions pass Imperas tests
2021-07-11 22:06:33 +00:00
else if (funct7 == 7'b1101000 && rs2 == 5'b00010) name = "FCVT.S.L";
else if (funct7 == 7'b1101000 && rs2 == 5'b00011) name = "FCVT.S.LU";
else if (funct7 == 7'b1100001 && rs2 == 5'b00000) name = "FCVT.W.D";
else if (funct7 == 7'b1100001 && rs2 == 5'b00001) name = "FCVT.WU.D";
else if (funct7 == 7'b1100001 && rs2 == 5'b00010) name = "FCVT.L.D";
else if (funct7 == 7'b1100001 && rs2 == 5'b00011) name = "FCVT.LU.D";
else if (funct7 == 7'b1101001 && rs2 == 5'b00000) name = "FCVT.D.W";
else if (funct7 == 7'b1101001 && rs2 == 5'b00001) name = "FCVT.D.WU";
else if (funct7 == 7'b1101001 && rs2 == 5'b00010) name = "FCVT.D.L";
else if (funct7 == 7'b1101001 && rs2 == 5'b00011) name = "FCVT.D.LU";
else if (funct7 == 7'b0100000 && rs2 == 5'b00001) name = "FCVT.S.D";
else if (funct7 == 7'b0100001 && rs2 == 5'b00000) name = "FCVT.D.S";
floating point infinite loop removed from imperas tests
2021-05-18 14:42:51 +00:00
else name = "ILLEGAL";
10'b0000111_010: name = "FLW";
10'b0100111_010: name = "FSW";
FMV.D.X imperas test passes
2021-05-21 02:17:59 +00:00
10'b0000111_011: name = "FLD";
10'b0100111_011: name = "FSD";
Initial Checkin
2021-01-15 04:37:51 +00:00
default: name = "ILLEGAL";
endcase
endmodule
Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
2021-07-04 05:19:38 +00:00
module logging(
input logic clk, reset,
input logic [31:0] HADDR,
input logic [1:0] HTRANS);
always @(posedge clk)
if (HTRANS != 2'b00 && HADDR == 0)
Progress towards the test bench flush.
2021-07-12 19:22:13 +00:00
$display("%t Warning: access to memory address 0\n", $realtime);
Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
2021-07-04 05:19:38 +00:00
endmodule
Progress towards the test bench flush.
2021-07-12 19:22:13 +00:00
module DCacheFlushFSM
(input logic clk,
input logic reset,
input logic start,
output logic done);
localparam integer numlines = testbench.dut.hart.lsu.dcache.NUMLINES;
localparam integer numways = testbench.dut.hart.lsu.dcache.NUMWAYS;
localparam integer blockbytelen = testbench.dut.hart.lsu.dcache.BLOCKBYTELEN;
localparam integer numwords = testbench.dut.hart.lsu.dcache.BLOCKLEN/`XLEN;
localparam integer lognumlines = $clog2(numlines);
localparam integer logblockbytelen = $clog2(blockbytelen);
localparam integer lognumways = $clog2(numways);
localparam integer tagstart = lognumlines + logblockbytelen;
Team work on solving the dcache data inconsistency problem.
2021-07-13 04:46:32 +00:00
genvar index, way, cacheWord;
logic [`XLEN-1:0] CacheData [numways-1:0] [numlines-1:0] [numwords-1:0];
Modularized the shadow memory to reduce performance hit.
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logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [numwords-1:0];
logic CacheValid [numways-1:0] [numlines-1:0] [numwords-1:0];
logic CacheDirty [numways-1:0] [numlines-1:0] [numwords-1:0];
Team work on solving the dcache data inconsistency problem.
2021-07-13 04:46:32 +00:00
logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [numwords-1:0];
genvar adr;
Progress towards the test bench flush.
2021-07-12 19:22:13 +00:00
Team work on solving the dcache data inconsistency problem.
2021-07-13 04:46:32 +00:00
logic [`XLEN-1:0] ShadowRAM[`TIM_BASE>>(1+`XLEN/32):(`TIM_RANGE+`TIM_BASE)>>1+(`XLEN/32)];
generate
for(index = 0; index < numlines; index++) begin
for(way = 0; way < numways; way++) begin
for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin
Also changed the shadow ram's dcache copy widths. Merge branch 'dcache' into main
2021-07-16 19:21:09 +00:00
copyShadow #(.tagstart(tagstart),
.logblockbytelen(logblockbytelen))
Modularized the shadow memory to reduce performance hit.
2021-07-13 15:55:57 +00:00
copyShadow(.clk,
.start,
.tag(testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.CacheTagMem.StoredData[index]),
.valid(testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.ValidBits[index]),
.dirty(testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.DirtyBits[index]),
.data(testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.word[cacheWord].CacheDataMem.StoredData[index]),
Also changed the shadow ram's dcache copy widths. Merge branch 'dcache' into main
2021-07-16 19:21:09 +00:00
.index(index),
.cacheWord(cacheWord),
Modularized the shadow memory to reduce performance hit.
2021-07-13 15:55:57 +00:00
.CacheData(CacheData[way][index][cacheWord]),
.CacheAdr(CacheAdr[way][index][cacheWord]),
.CacheTag(CacheTag[way][index][cacheWord]),
.CacheValid(CacheValid[way][index][cacheWord]),
.CacheDirty(CacheDirty[way][index][cacheWord]));
Progress towards the test bench flush.
2021-07-12 19:22:13 +00:00
end
end
Team work on solving the dcache data inconsistency problem.
2021-07-13 04:46:32 +00:00
end
endgenerate
Also changed the shadow ram's dcache copy widths. Merge branch 'dcache' into main
2021-07-16 19:21:09 +00:00
/* -----\/----- EXCLUDED -----\/-----
.Adr(((testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.CacheTagMem.StoredData[index] << tagstart)
+ (index << logblockbytelen) + (cacheWord << $clog2(`XLEN/8)))),
-----/\----- EXCLUDED -----/\----- */
Modularized the shadow memory to reduce performance hit.
2021-07-13 15:55:57 +00:00
Team work on solving the dcache data inconsistency problem.
2021-07-13 04:46:32 +00:00
integer i, j, k;
always @(posedge clk) begin
if (start) begin #1
Modularized the shadow memory to reduce performance hit.
2021-07-13 15:55:57 +00:00
#1
Team work on solving the dcache data inconsistency problem.
2021-07-13 04:46:32 +00:00
for(i = 0; i < numlines; i++) begin
for(j = 0; j < numways; j++) begin
Modularized the shadow memory to reduce performance hit.
2021-07-13 15:55:57 +00:00
for(k = 0; k < numwords; k++) begin
if (CacheValid[j][i][k] && CacheDirty[j][i][k]) begin
ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = CacheData[j][i][k];
Got the shadow ram cache flush working.
2021-07-13 15:03:47 +00:00
end
end
Team work on solving the dcache data inconsistency problem.
2021-07-13 04:46:32 +00:00
end
Progress towards the test bench flush.
2021-07-12 19:22:13 +00:00
end
Team work on solving the dcache data inconsistency problem.
2021-07-13 04:46:32 +00:00
end
Progress towards the test bench flush.
2021-07-12 19:22:13 +00:00
end
Got the shadow ram cache flush working.
2021-07-13 15:03:47 +00:00
flop #(1) doneReg(.clk(clk),
.d(start),
.q(done));
Progress towards the test bench flush.
2021-07-12 19:22:13 +00:00
Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
2021-07-04 05:19:38 +00:00
endmodule
Progress towards the test bench flush.
2021-07-12 19:22:13 +00:00
Modularized the shadow memory to reduce performance hit.
2021-07-13 15:55:57 +00:00
module copyShadow
Also changed the shadow ram's dcache copy widths. Merge branch 'dcache' into main
2021-07-16 19:21:09 +00:00
#(parameter tagstart, logblockbytelen)
Modularized the shadow memory to reduce performance hit.
2021-07-13 15:55:57 +00:00
(input logic clk,
input logic start,
input logic [`PA_BITS-1:tagstart] tag,
input logic valid, dirty,
input logic [`XLEN-1:0] data,
Also changed the shadow ram's dcache copy widths. Merge branch 'dcache' into main
2021-07-16 19:21:09 +00:00
input logic [32-1:0] index,
input logic [32-1:0] cacheWord,
Modularized the shadow memory to reduce performance hit.
2021-07-13 15:55:57 +00:00
output logic [`XLEN-1:0] CacheData,
output logic [`PA_BITS-1:0] CacheAdr,
output logic [`XLEN-1:0] CacheTag,
output logic CacheValid,
output logic CacheDirty);
Progress towards the test bench flush.
2021-07-12 19:22:13 +00:00
Modularized the shadow memory to reduce performance hit.
2021-07-13 15:55:57 +00:00
always_ff @(posedge clk) begin
if(start) begin
CacheTag = tag;
CacheValid = valid;
CacheDirty = dirty;
CacheData = data;
Also changed the shadow ram's dcache copy widths. Merge branch 'dcache' into main
2021-07-16 19:21:09 +00:00
CacheAdr = (tag << tagstart) + (index << logblockbytelen) + (cacheWord << $clog2(`XLEN/8));
Progress towards the test bench flush.
2021-07-12 19:22:13 +00:00
end
Modularized the shadow memory to reduce performance hit.
2021-07-13 15:55:57 +00:00
end
Progress towards the test bench flush.
2021-07-12 19:22:13 +00:00
Modularized the shadow memory to reduce performance hit.
2021-07-13 15:55:57 +00:00
endmodule
Progress towards the test bench flush.
2021-07-12 19:22:13 +00:00
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