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1554 Commits

Author SHA1 Message Date
David Harris
078ddfd341 Divider cleanup 2021-10-03 00:41:41 -04:00
David Harris
8f36297569 Added suffixes to more divider signals 2021-10-03 00:32:58 -04:00
bbracker
07ff0940a3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-03 00:30:49 -04:00
bbracker
a202c705cd checkpoint generator bugfixes 2021-10-03 00:30:04 -04:00
David Harris
dcbbee6623 More divider cleanup 2021-10-03 00:20:35 -04:00
David Harris
6aa2521959 Eliminated extra inversion for subtraction in divider 2021-10-03 00:10:12 -04:00
David Harris
371f9d9a4a Added more pipeline stage suffixes to divider 2021-10-03 00:06:57 -04:00
David Harris
24bb3f4baf Added more pipeline stage suffixes to divider 2021-10-02 22:54:01 -04:00
David Harris
3441991d93 Divider mostly cleaned up 2021-10-02 21:10:35 -04:00
David Harris
67690c2ed7 Partial divider cleanup 3 2021-10-02 21:00:13 -04:00
David Harris
775520c05a Partial divider cleanup 2 2021-10-02 20:57:54 -04:00
David Harris
fe69513bb7 Partial divider cleanup 2021-10-02 20:55:37 -04:00
David Harris
a86ce5cd37 Divider code cleanup 2021-10-02 10:41:09 -04:00
David Harris
d532bde931 Added negative edge triggered flop to save inputs; do absolute value in first cycle for signed division 2021-10-02 10:36:51 -04:00
David Harris
d4437b842a Divider code cleanup 2021-10-02 10:13:49 -04:00
David Harris
0e0e204d3d Moved negating divider otuput to M stage 2021-10-02 10:03:02 -04:00
David Harris
735132191c Moved muldiv result selection to M stage for performance 2021-10-02 09:38:02 -04:00
David Harris
73d852b1ef Divide performs 2 steps per cycle 2021-10-02 09:19:25 -04:00
David Harris
35e5a5cef3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-30 23:15:34 -04:00
bbracker
5022647041 Revert "first attempt at verilog side of checkpoint functionality" 
This reverts commit f6ef8e5656.
 2021-09-30 20:45:26 -04:00
David Harris
a39e14663d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-30 20:07:43 -04:00
David Harris
a8573a27d4 Integer Divide/Rem passing all regression. 2021-09-30 20:07:22 -04:00
David Harris
953c8931ed RV32 div/rem working signed and unsigned 2021-09-30 15:24:43 -04:00
David Harris
e1ad732178 SRT Division unsigned passing Imperas tests 2021-09-30 12:17:24 -04:00
bbracker
f6ef8e5656 first attempt at verilog side of checkpoint functionality 2021-09-28 23:17:58 -04:00
bbracker
a47448c4d0 first attemtpt at checkpoint infrastructure 2021-09-28 22:33:47 -04:00
bbracker
2ffdbdf6d2 condense testbench code; debug_level of 0 means don't check at all 2021-09-27 03:03:11 -04:00
bbracker
441759b81c switch testbench-linux's interrupts from xcause to mip and improve warning messages 2021-09-22 12:33:11 -04:00
bbracker
b1c2a77fc2 update setup scripts to new testvector files 2021-09-22 12:31:10 -04:00
kipmacsaigoren
afd73ddada Merge branch 'ppa' into main 2021-09-20 01:01:47 -05:00
Ross Thompson
d09b381183 Fixed the amo on dcache miss cpu stall issue. 2021-09-17 22:15:03 -05:00
Ross Thompson
99d675b872 Finished adding the d cache flush. Required ensuring the write data, address, and size are 
correct when transmitting to AHBLite interface.
 2021-09-17 13:03:04 -05:00
Kip Macsai-Goren
f1981a1267 more input changes on prioirty thermometer. passes lint 2021-09-17 13:07:21 -04:00
kipmacsaigoren
f48c780ec2 added new fun ways of putting inputs into the priority thermometer 2021-09-17 12:00:38 -05:00
Ross Thompson
8fa287a449 The E stage needs to be flushed on InvalidateICacheM. FlushM should be asserted. 2021-09-17 10:33:57 -05:00
Ross Thompson
b92070a67a Updated Dcache to fully support flush. This appears to work. 
Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
 2021-09-17 10:25:21 -05:00
Ross Thompson
d4398c23fb Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes. 2021-09-16 18:32:29 -05:00
Ross Thompson
55cbd957f0 Added counters to walk through d cache flush. 2021-09-16 17:12:51 -05:00
Ross Thompson
4ca0c0ea7d Added flush controls to cachway. 2021-09-16 16:56:48 -05:00
Ross Thompson
eb7b5f1d63 Added invalidate to icache. 2021-09-16 16:15:54 -05:00
bbracker
92ddc9b20a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-15 17:31:11 -04:00
bbracker
b1be8f4858 fix regression 2021-09-15 17:30:59 -04:00
kipmacsaigoren
437f2d5814 changed priority circuits for synthesis and light cleanup 2021-09-15 12:24:24 -05:00
David Harris
72c1cc33f5 Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression. 2021-09-15 13:14:00 -04:00
bbracker
f94a13e242 created script to determine which functions are most frequently used 2021-09-14 19:41:05 -04:00
David Harris
e32ab128e9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-13 12:41:07 -04:00
David Harris
654f3d1940 Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64 2021-09-13 12:40:40 -04:00
Ross Thompson
d4c87d17b2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-09-13 09:41:34 -05:00
David Harris
1847198da9 Cleaned up wally-arch test scripts 2021-09-13 00:02:32 -04:00
David Harris
b2fe8eddc0 Restored old integer divider 2021-09-12 22:07:52 -04:00
Ross Thompson
144003cb41 FPGA test bench and test program. 2021-09-12 20:41:54 -05:00
David Harris
1f6e4c71fc Modified rxfull determination in UART, started division 2021-09-12 20:00:24 -04:00
Ross Thompson
225657b8f9 Fixed bug with or_rows. 
If ROWS == 1 then the output was always X.  Fixed by adding if to check if ROWS==1.
 2021-09-11 15:51:11 -05:00
Ross Thompson
3b12235954 Fixed FPGA synthesis bug in the fpdiv fsm. Was creating latches. 2021-09-11 15:40:27 -05:00
Ross Thompson
3ff8d0095d Fixed dcache to prevent latches in FPGA synthesized design. 2021-09-11 12:03:48 -05:00
Ross Thompson
29efd1d222 Third attempt at fixing the write enables for the icache cacheway. 2021-09-09 15:08:10 -05:00
Ross Thompson
230c794edd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Refixed some bit width issues in the icache.
 2021-09-09 12:44:02 -05:00
Ross Thompson
90f2821bea fixed some lint bugs. 2021-09-09 12:38:57 -05:00
bbracker
886e8125db Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-09 13:22:31 -04:00
bbracker
83520aeb42 changed fix_mem to not use hardcoded file names 2021-09-09 13:22:24 -04:00
David Harris
cb624fe679 Lint cleaning, riscv-arch-test testing 2021-09-09 11:05:12 -04:00
David Harris
a31828e925 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-08 16:00:12 -04:00
David Harris
30e2ec3987 Added testbench-arch for riscv-arch-test suite 2021-09-08 15:59:40 -04:00
Ross Thompson
8141a515bb Changed configs to support 4 ways set associative caches. 2021-09-08 12:52:49 -05:00
Ross Thompson
6606eea27e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-09-08 12:47:03 -05:00
Ross Thompson
5bc90ef32f Slight modification to wave file. 2021-09-08 10:40:46 -05:00
bbracker
5e9a39e755 fixed bug where M mode was sensitive to S mode traps 2021-09-07 19:14:39 -04:00
bbracker
b3f00f2682 make testbench successfully deactivate TimerIntM so as to create a nice pulse 2021-09-07 15:36:47 -04:00
Ross Thompson
150a73d6cf Set associate icache working, but way 0 is never written. 2021-09-07 12:46:16 -05:00
bbracker
28fed18421 No longer forcing CSRReadValM because that can feedback to corrupt some CSRs 2021-09-06 22:59:54 -04:00
Ross Thompson
00f50184d8 Changed name of memory in icache. 2021-09-06 20:54:52 -05:00
bbracker
0646bf2b90 help in case a script is run accidentally 2021-09-06 16:23:45 -04:00
bbracker
a13b561759 modified testbench to not allow Wally to generate its own interrupts (because of fundamental interrupt imprecision limitations) 2021-09-04 19:49:26 -04:00
bbracker
58d478eb23 restore functionality of being able to turn on waves at a certain instruction count; restore linux-waves.do because wave.do seems to be in disrepair 2021-09-04 19:45:04 -04:00
bbracker
0004f647ec switching over to hopefully more consistent QEMU simulated clock 2021-09-04 19:43:39 -04:00
bbracker
6155716de4 replace triple gdb breakpoint continue with a double breakpoint ignore in hopes of improving parsing 2021-09-04 19:41:55 -04:00
James E. Stine
5bc3569b0e Not sure I understand the Misaligned hptw - seems like a bug and should be L1_ADR instead of L0_ADR 2021-09-03 10:26:38 -05:00
bbracker
4a938e493e output trace to linux-testvectors folder 2021-09-01 17:37:46 -04:00
Ross Thompson
5c2deab4e4 Partial multiway set associative icache. 2021-08-30 10:49:24 -05:00
Katherine Parry
7607adc951 FMA cleanup 2021-08-28 10:53:35 -04:00
Ross Thompson
4b0344898b Fixed bugs I introduced to the icache. 2021-08-27 15:00:40 -05:00
Ross Thompson
2dff72d9e9 Renamed PCMux (icache) to SelAdr to match dcache. 
Removed unused cache files.
 2021-08-27 11:14:10 -05:00
Ross Thompson
de9e234ffa Modified icache to no longer need StallF in the PCMux logic. Instead this is handled in the icachefsm. 
One downside is it increases the icache complexity.  However it also fixes an untested bug.  If a region
was uncacheable it would have been possible for the request to be made multiple times.  Now that is
not possible.  Additionally spills were oscillating between the spill hit states without this change.
The impact was 'benign' as the final spilled instruction always had the correct upper 16 bits.
 2021-08-27 11:03:36 -05:00
Ross Thompson
62d91e9ea1 Renamed ICacheCntrl to icachefsm. 2021-08-26 15:57:17 -05:00
Ross Thompson
cbb47956cb Swapped out the icachemem for cacheway. cacheway is modified to optionally support dirty bits. 2021-08-26 15:43:02 -05:00
Ross Thompson
b230d4daec Finished moving data path logic from the ICacheCntrl.sv to icache.sv. 2021-08-26 13:06:24 -05:00
Ross Thompson
b3849d8abb Moved data path logic from icacheCntrl to icache. 2021-08-26 10:58:19 -05:00
Ross Thompson
c83f0a2e99 Removed unused logic in icache. 2021-08-26 10:49:54 -05:00
Ross Thompson
642efbb563 Converted the icache type from logic to state type. 2021-08-26 10:41:42 -05:00
Ross Thompson
b5d6c4fb46 Additional cleanup of ahblite. 2021-08-25 22:53:20 -05:00
Ross Thompson
bf312bb37c Removed amo logic from ahblite. Removed many unused signals from ahblite. 2021-08-25 22:45:13 -05:00
Ross Thompson
939ff663a5 Forgot to include a few files in the last few commits. 
Also reorganized the dcache by read cpu path, write cpu path, and bus interface path.
Changed i/o names on subwordread to match signals in dcache.
 2021-08-25 22:30:05 -05:00
Ross Thompson
d2b3b7345e Moved dcache fsm to separate module. 2021-08-25 21:37:10 -05:00
Ross Thompson
7be0a73db1 Moved LRU and storage for the LRU into a single module. Also found a subtle bug with the update address used to write the cache's memory. 
This was correct for the LRU but incorrect for the data, tag, valid, and dirty storage.
 2021-08-25 21:09:42 -05:00
Ross Thompson
b5eba44417 Replaced dcache generate ORing with or_rows. 2021-08-25 13:46:36 -05:00
Ross Thompson
83cc0266b2 Rename of DCacheMem to cacheway. 
simplified dcache names.
 2021-08-25 13:33:15 -05:00
Ross Thompson
c48556836b Removed generate around the dcache memories. 2021-08-25 13:27:26 -05:00
Ross Thompson
7139279e50 Moved more logic inside the dcache memory. 2021-08-25 13:17:07 -05:00
Ross Thompson
a99b5f648b partial dcache reorg. 2021-08-25 12:42:05 -05:00
Ross Thompson
699053bab0 Updated linux test bench documenation and scripts. 2021-08-25 10:54:47 -05:00