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1049 Commits

Author SHA1 Message Date
David Harris
cc41d40d61 Divider cleaup 2021-10-03 11:22:34 -04:00
David Harris
3398328bf1 Divider cleanup 2021-10-03 11:16:48 -04:00
David Harris
9809e57d0c Replacing XE and DE with SrcAE and SrcBE in divider 2021-10-03 11:11:53 -04:00
David Harris
bf0061be66 Reduced cycle count for DIVW/DIVUW by two 2021-10-03 09:42:22 -04:00
David Harris
bd61ec544b Divider comments cleanup 2021-10-03 01:12:40 -04:00
David Harris
30ec68d567 Parameterized number of bits per cycle for integer division 2021-10-03 01:10:15 -04:00
David Harris
078ddfd341 Divider cleanup 2021-10-03 00:41:41 -04:00
David Harris
8f36297569 Added suffixes to more divider signals 2021-10-03 00:32:58 -04:00
David Harris
dcbbee6623 More divider cleanup 2021-10-03 00:20:35 -04:00
David Harris
6aa2521959 Eliminated extra inversion for subtraction in divider 2021-10-03 00:10:12 -04:00
David Harris
371f9d9a4a Added more pipeline stage suffixes to divider 2021-10-03 00:06:57 -04:00
David Harris
24bb3f4baf Added more pipeline stage suffixes to divider 2021-10-02 22:54:01 -04:00
David Harris
3441991d93 Divider mostly cleaned up 2021-10-02 21:10:35 -04:00
David Harris
67690c2ed7 Partial divider cleanup 3 2021-10-02 21:00:13 -04:00
David Harris
775520c05a Partial divider cleanup 2 2021-10-02 20:57:54 -04:00
David Harris
fe69513bb7 Partial divider cleanup 2021-10-02 20:55:37 -04:00
David Harris
a86ce5cd37 Divider code cleanup 2021-10-02 10:41:09 -04:00
David Harris
d532bde931 Added negative edge triggered flop to save inputs; do absolute value in first cycle for signed division 2021-10-02 10:36:51 -04:00
David Harris
d4437b842a Divider code cleanup 2021-10-02 10:13:49 -04:00
David Harris
0e0e204d3d Moved negating divider otuput to M stage 2021-10-02 10:03:02 -04:00
David Harris
735132191c Moved muldiv result selection to M stage for performance 2021-10-02 09:38:02 -04:00
David Harris
73d852b1ef Divide performs 2 steps per cycle 2021-10-02 09:19:25 -04:00
David Harris
35e5a5cef3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-30 23:15:34 -04:00
bbracker
5022647041 Revert "first attempt at verilog side of checkpoint functionality" 
This reverts commit f6ef8e5656.
 2021-09-30 20:45:26 -04:00
David Harris
a39e14663d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-30 20:07:43 -04:00
David Harris
a8573a27d4 Integer Divide/Rem passing all regression. 2021-09-30 20:07:22 -04:00
David Harris
953c8931ed RV32 div/rem working signed and unsigned 2021-09-30 15:24:43 -04:00
David Harris
e1ad732178 SRT Division unsigned passing Imperas tests 2021-09-30 12:17:24 -04:00
bbracker
f6ef8e5656 first attempt at verilog side of checkpoint functionality 2021-09-28 23:17:58 -04:00
kipmacsaigoren
afd73ddada Merge branch 'ppa' into main 2021-09-20 01:01:47 -05:00
Ross Thompson
d09b381183 Fixed the amo on dcache miss cpu stall issue. 2021-09-17 22:15:03 -05:00
Ross Thompson
99d675b872 Finished adding the d cache flush. Required ensuring the write data, address, and size are 
correct when transmitting to AHBLite interface.
 2021-09-17 13:03:04 -05:00
Kip Macsai-Goren
f1981a1267 more input changes on prioirty thermometer. passes lint 2021-09-17 13:07:21 -04:00
kipmacsaigoren
f48c780ec2 added new fun ways of putting inputs into the priority thermometer 2021-09-17 12:00:38 -05:00
Ross Thompson
8fa287a449 The E stage needs to be flushed on InvalidateICacheM. FlushM should be asserted. 2021-09-17 10:33:57 -05:00
Ross Thompson
b92070a67a Updated Dcache to fully support flush. This appears to work. 
Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
 2021-09-17 10:25:21 -05:00
Ross Thompson
d4398c23fb Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes. 2021-09-16 18:32:29 -05:00
Ross Thompson
55cbd957f0 Added counters to walk through d cache flush. 2021-09-16 17:12:51 -05:00
Ross Thompson
4ca0c0ea7d Added flush controls to cachway. 2021-09-16 16:56:48 -05:00
Ross Thompson
eb7b5f1d63 Added invalidate to icache. 2021-09-16 16:15:54 -05:00
kipmacsaigoren
437f2d5814 changed priority circuits for synthesis and light cleanup 2021-09-15 12:24:24 -05:00
David Harris
72c1cc33f5 Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression. 2021-09-15 13:14:00 -04:00
David Harris
654f3d1940 Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64 2021-09-13 12:40:40 -04:00
David Harris
b2fe8eddc0 Restored old integer divider 2021-09-12 22:07:52 -04:00
David Harris
1f6e4c71fc Modified rxfull determination in UART, started division 2021-09-12 20:00:24 -04:00
Ross Thompson
225657b8f9 Fixed bug with or_rows. 
If ROWS == 1 then the output was always X.  Fixed by adding if to check if ROWS==1.
 2021-09-11 15:51:11 -05:00
Ross Thompson
3b12235954 Fixed FPGA synthesis bug in the fpdiv fsm. Was creating latches. 2021-09-11 15:40:27 -05:00
Ross Thompson
3ff8d0095d Fixed dcache to prevent latches in FPGA synthesized design. 2021-09-11 12:03:48 -05:00
Ross Thompson
29efd1d222 Third attempt at fixing the write enables for the icache cacheway. 2021-09-09 15:08:10 -05:00
Ross Thompson
230c794edd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Refixed some bit width issues in the icache.
 2021-09-09 12:44:02 -05:00
Ross Thompson
90f2821bea fixed some lint bugs. 2021-09-09 12:38:57 -05:00
David Harris
cb624fe679 Lint cleaning, riscv-arch-test testing 2021-09-09 11:05:12 -04:00
David Harris
a31828e925 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-09-08 16:00:12 -04:00
David Harris
30e2ec3987 Added testbench-arch for riscv-arch-test suite 2021-09-08 15:59:40 -04:00
Ross Thompson
6606eea27e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-09-08 12:47:03 -05:00
bbracker
5e9a39e755 fixed bug where M mode was sensitive to S mode traps 2021-09-07 19:14:39 -04:00
Ross Thompson
150a73d6cf Set associate icache working, but way 0 is never written. 2021-09-07 12:46:16 -05:00
Ross Thompson
00f50184d8 Changed name of memory in icache. 2021-09-06 20:54:52 -05:00
James E. Stine
5bc3569b0e Not sure I understand the Misaligned hptw - seems like a bug and should be L1_ADR instead of L0_ADR 2021-09-03 10:26:38 -05:00
Ross Thompson
5c2deab4e4 Partial multiway set associative icache. 2021-08-30 10:49:24 -05:00
Katherine Parry
7607adc951 FMA cleanup 2021-08-28 10:53:35 -04:00
Ross Thompson
4b0344898b Fixed bugs I introduced to the icache. 2021-08-27 15:00:40 -05:00
Ross Thompson
2dff72d9e9 Renamed PCMux (icache) to SelAdr to match dcache. 
Removed unused cache files.
 2021-08-27 11:14:10 -05:00
Ross Thompson
de9e234ffa Modified icache to no longer need StallF in the PCMux logic. Instead this is handled in the icachefsm. 
One downside is it increases the icache complexity.  However it also fixes an untested bug.  If a region
was uncacheable it would have been possible for the request to be made multiple times.  Now that is
not possible.  Additionally spills were oscillating between the spill hit states without this change.
The impact was 'benign' as the final spilled instruction always had the correct upper 16 bits.
 2021-08-27 11:03:36 -05:00
Ross Thompson
62d91e9ea1 Renamed ICacheCntrl to icachefsm. 2021-08-26 15:57:17 -05:00
Ross Thompson
cbb47956cb Swapped out the icachemem for cacheway. cacheway is modified to optionally support dirty bits. 2021-08-26 15:43:02 -05:00
Ross Thompson
b230d4daec Finished moving data path logic from the ICacheCntrl.sv to icache.sv. 2021-08-26 13:06:24 -05:00
Ross Thompson
b3849d8abb Moved data path logic from icacheCntrl to icache. 2021-08-26 10:58:19 -05:00
Ross Thompson
c83f0a2e99 Removed unused logic in icache. 2021-08-26 10:49:54 -05:00
Ross Thompson
642efbb563 Converted the icache type from logic to state type. 2021-08-26 10:41:42 -05:00
Ross Thompson
b5d6c4fb46 Additional cleanup of ahblite. 2021-08-25 22:53:20 -05:00
Ross Thompson
bf312bb37c Removed amo logic from ahblite. Removed many unused signals from ahblite. 2021-08-25 22:45:13 -05:00
Ross Thompson
939ff663a5 Forgot to include a few files in the last few commits. 
Also reorganized the dcache by read cpu path, write cpu path, and bus interface path.
Changed i/o names on subwordread to match signals in dcache.
 2021-08-25 22:30:05 -05:00
Ross Thompson
d2b3b7345e Moved dcache fsm to separate module. 2021-08-25 21:37:10 -05:00
Ross Thompson
7be0a73db1 Moved LRU and storage for the LRU into a single module. Also found a subtle bug with the update address used to write the cache's memory. 
This was correct for the LRU but incorrect for the data, tag, valid, and dirty storage.
 2021-08-25 21:09:42 -05:00
Ross Thompson
b5eba44417 Replaced dcache generate ORing with or_rows. 2021-08-25 13:46:36 -05:00
Ross Thompson
83cc0266b2 Rename of DCacheMem to cacheway. 
simplified dcache names.
 2021-08-25 13:33:15 -05:00
Ross Thompson
c48556836b Removed generate around the dcache memories. 2021-08-25 13:27:26 -05:00
Ross Thompson
7139279e50 Moved more logic inside the dcache memory. 2021-08-25 13:17:07 -05:00
Ross Thompson
a99b5f648b partial dcache reorg. 2021-08-25 12:42:05 -05:00
David Harris
cb13e36d20 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-08-25 06:47:20 -04:00
David Harris
cf1e458ccf simplified or_rows generation and renamed oneHotDecoder to onehotdecoder 2021-08-25 06:46:41 -04:00
Ross Thompson
bb3e94d68a Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage. 2021-08-23 15:46:17 -05:00
Ross Thompson
97653e1aea Wally previously was overcounting retired instructions when they were flushed. 
InstrValidM was used to control when the counter was updated.  However this is
not suppress the counter when the instruction is flushed in the M stage.
 2021-08-23 12:24:03 -05:00
Ross Thompson
b6e2710f5d Confirmed David's changes to the interrupt code. 
When a timer interrupt occurs it should be routed to the machine interrupt
pending MTIP even if MIDELEG[5] = 1 when the current privilege mode is
Machine.  This is true for all the interrupts. The interrupt should not be
masked even though it is delegated to a lower privilege.  Since the CPU
is currently in machine mode the interrupt must be taken if MIE.

Additionally added a new qemu script which pipes together all the parsing and
post processing scripts to produce the singular all.txt trace without the
massivie intermediate files.
 2021-08-22 21:36:31 -05:00
David Harris
696be3ff68 possible interrupt code 2021-08-22 17:02:40 -04:00
Ross Thompson
95f5ebaf30 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-08-17 16:06:54 -05:00
Ross Thompson
d3417e309b Minor changes to dcache. 2021-08-17 15:22:10 -05:00
Katherine Parry
facd4062d0 all conversions go through the execute stage result mux 2021-08-16 13:06:09 -04:00
Ross Thompson
66ad510abf Modified the hptw's simulation error message so that synthesis does not attempt to include this statement. 2021-08-16 10:02:29 -05:00
Ross Thompson
4c8ea89f15 Fixed syntax errors in some floating point modules. This came up in 
Xilinx synthesis.
 2021-08-15 16:48:49 -05:00
Ross Thompson
4f1f9d6e37 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-08-13 17:23:04 -05:00
Ross Thompson
4f3f26c5cb Switched ExceptionM to dcache to be just exceptions. 
Added test bench logic to hold forces until the W stage is unstalled.
 2021-08-13 15:53:50 -05:00
Katherine Parry
567260751a move some FPU select muxs to execute stage 2021-08-13 14:41:22 -04:00
Ross Thompson
272425c41f Added documentation about how the dcache and ptw interact. 2021-08-12 18:05:36 -05:00
Ross Thompson
618cc18903 Optimized subwordread to reduce critical path from 8 muxes to 5 muxes + 1 AND gate. 2021-08-12 13:36:33 -05:00
Ross Thompson
4dfe326761 Removed unused states from dcache fsm. 2021-08-11 17:06:09 -05:00
Ross Thompson
192392b524 Modified invalid plic reads to return 0 rather than deadbeaf. 2021-08-11 16:56:22 -05:00
Ross Thompson
d0afa397ba Simplified Dcache by sharing the read data mux with the victim selection mux. 2021-08-11 16:55:55 -05:00
Ross Thompson
74e5b60819 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-08-10 13:36:29 -05:00
Ross Thompson
05a32508eb Dcache and LSU clean up. 2021-08-10 13:36:21 -05:00
Katherine Parry
21555c392f LZA added to FMA and attemting a merged FMA and adder in synthesis 2021-08-10 13:57:16 -04:00
Ross Thompson
467e24c05c Fixed another bug with the atomic instrucitons implemention in the dcache. 2021-08-08 22:50:31 -05:00
Ross Thompson
20a04d8cee Fixed another bug with AMO. If the CPU stalled as an AMO was finishing, the write to the 
cache's SRAM would occur.  Then in the next cycle the SRAM would be reread while stalled
providing the new update dated rather than the correct older value.
 2021-08-08 11:42:10 -05:00
Ross Thompson
25533bdc49 Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic. 
Fixed logic for trace update in the M and W stages.  The M stage should not update if there
is an instruction fault.
 2021-08-08 00:28:18 -05:00
Ross Thompson
d430659983 fixed the read timer issue but we still have problems with interrupts and i/o devices. 2021-08-06 10:16:06 -05:00
Ross Thompson
b7fc737d93 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-30 17:57:13 -05:00
Ross Thompson
89a7b38f79 Removed 1 cycle delay on store miss. 
Changed some logic to partially support atomics.
 2021-07-30 14:00:51 -05:00
Katherine Parry
d8ca70fc45 all fpu units use the unpacking unit 2021-07-28 23:49:21 -04:00
Ross Thompson
c60a1fed69 Fixed bug which caused stores to take an extra clock cycle. 2021-07-26 12:22:53 -05:00
Ross Thompson
5b376b9846 Fixed bug with the compressed immediate generation. Several formats should zero extend. 2021-07-26 11:55:31 -05:00
Ross Thompson
ce29d0f00f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
 2021-07-26 11:55:00 -05:00
Ross Thompson
0291d987da Added additional interlock for itlb miss -> instrPageFault with concurrent memory operation. 2021-07-25 23:14:28 -05:00
Katherine Parry
8198e8162a fixed some fpu lint errors 2021-07-24 16:41:12 -04:00
Katherine Parry
85d240c2a5 fpu cleanup 2021-07-24 15:00:56 -04:00
Katherine Parry
67ab0b165c fpu cleanup 2021-07-24 14:59:57 -04:00
kipmacsaigoren
3bb6c8b32f Cleaned up priority thermometer verilog. passses regression, ideally shortens critical path through pmp's 2021-07-23 11:57:58 -05:00
David Harris
5306d42bfe Removed LEVELx states from HPTW 2021-07-23 08:11:15 -04:00
Ross Thompson
00f798b37e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-22 19:42:32 -05:00
Ross Thompson
32ec457e09 Removed the hardware page table walker fault state from the icache so that the icache will only unstall CPU for 1 cycle. 
In the dcache we added a register to save the load read data in the event an itlb miss occurs concurrently with
the load in the memory stage.  Under this situation we need to record the load ReadDataM into a temporary register,
SavedReadDataM.  At this time the CPU is stall; however the walker is going to change the address in the dcache
which destroys this data.  When leaving the PTW_READY state via a walker instruction fault or ITLB write we select
this SavedReadDataM so that the CPU can capture it.
 2021-07-22 19:42:19 -05:00
David Harris
427063ee05 Minor unpacking cleanup 2021-07-22 17:52:37 -04:00
Ross Thompson
007812dbdc Moved the ReadDataW register into the datapath. 
The StallW from the hazard unit controls this.
Previously it was in the dcache and controlled by both the HPTW and hazard unit.
This caused an issue when the CPU expected the data to stay constant while
stalled, but the HPTW was causing the data to be modified.
 2021-07-22 14:52:03 -05:00
Ross Thompson
00858cd401 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-22 14:05:08 -05:00
Ross Thompson
936e034be9 Fixed bug with the itlb fault not dcache ptw ready state to ready state. 2021-07-22 14:04:56 -05:00
David Harris
0822d46e97 Move Z sign swapping out of unpacker 2021-07-22 14:32:38 -04:00
David Harris
85aaa4c6d7 Move Z=0 mux out of unpacker. 2021-07-22 14:28:55 -04:00
David Harris
c04f40d6e5 Move Z=0 mux out of unpacker. 2021-07-22 14:22:28 -04:00
David Harris
625d925369 Partial work on Unpacking exponents to larger word size. FCVT and FMA are presently broken. 2021-07-22 14:18:27 -04:00
David Harris
f4b45adf44 Simplify unpacker 2021-07-22 13:42:16 -04:00
David Harris
02f0c67e6f Simplify unpacker 2021-07-22 13:40:42 -04:00
David Harris
2f23ca2b77 Removed Assumed1 from FPU interface 2021-07-22 13:04:47 -04:00
David Harris
926ffc8a15 Simplified interface to fclassify and fsgn (fixed) 2021-07-22 12:33:38 -04:00
David Harris
ae29eaa98d Simplified interface to fclassify and fsgn 2021-07-22 12:30:46 -04:00
Ross Thompson
42fe5ceee3 Cleaned up icache and dcache. 2021-07-22 11:06:44 -05:00
Ross Thompson
89e22bc5e8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-22 10:38:24 -05:00
Ross Thompson
e907d57340 Tested all numbers of ways for dcache 1, 2, 4, and 8. 2021-07-22 10:38:07 -05:00
bbracker
9dcd5d3622 fix UART RX FIFO bug where tail pointer can overtake head pointer 2021-07-22 02:09:41 -04:00
Ross Thompson
1e88784bd4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-21 16:44:32 -05:00
Kip Macsai-Goren
bb8ec549a7 fixed issue with tlbflush remaining high during a stalled sfence instruction 2021-07-21 17:43:36 -04:00
Ross Thompson
aa624625bc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-21 16:39:07 -05:00
Ross Thompson
1f0ff804cf Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-21 14:56:30 -05:00
Ross Thompson
511c36fb1b Improved address bus names and usages in the walker, dcache, and tlbs. 
Merge branch 'walkerEnhance' into main
 2021-07-21 14:55:09 -05:00
Ross Thompson
abe57e3fd0 Added comment about better muxing. 2021-07-21 14:40:14 -05:00
Ross Thompson
3d79dc51bb 4 way set associative is now working. 2021-07-21 14:01:14 -05:00
Kip Macsai-Goren
e59490d032 Fixed TLB parameterization and valid bit flop to correctly do instr page faults 2021-07-21 14:44:43 -04:00
Katherine Parry
59f79722ab FDIV and FSQRT work 2021-07-21 14:08:14 -04:00
Ross Thompson
39fc9278ba Fixed remaining bugs in 2 way set associative dcache. 2021-07-21 10:35:23 -05:00
Ross Thompson
ba3aed8760 Finally fixed bug with the set associative design. The issue was not in the LRU but instead in the way selection mux. 
Also forgot to include cacheLRU.sv file.
 2021-07-20 23:17:42 -05:00
Katherine Parry
61f81bb76e FMA parameterized 2021-07-20 22:04:21 -04:00
Ross Thompson
8d0a552b5b Partially working 2 way set associative d cache. 2021-07-20 17:51:42 -05:00