Ross Thompson bb3e94d68a Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage.		2021-08-23 15:46:17 -05:00
..
cache	Minor changes to dcache.	2021-08-17 15:22:10 -05:00
ebu	moved subwordread to lsu	2021-07-17 20:37:20 -04:00
fpu	all conversions go through the execute stage result mux	2021-08-16 13:06:09 -04:00
generic	renamed or_rows.sv	2021-07-16 20:17:03 -04:00
hazard	Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage.	2021-08-23 15:46:17 -05:00
ieu	Moved the ReadDataW register into the datapath.	2021-07-22 14:52:03 -05:00
ifu	Fixed bug with the compressed immediate generation. Several formats should zero extend.	2021-07-26 11:55:31 -05:00
lsu	Optimized subwordread to reduce critical path from 8 muxes to 5 muxes + 1 AND gate.	2021-08-12 13:36:33 -05:00
mmu	Modified the hptw's simulation error message so that synthesis does not attempt to include this statement.	2021-08-16 10:02:29 -05:00
muldiv	Fixed syntax errors in some floating point modules. This came up in	2021-08-15 16:48:49 -05:00
privileged	Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage.	2021-08-23 15:46:17 -05:00
uncore	Modified invalid plic reads to return 0 rather than deadbeaf.	2021-08-11 16:56:22 -05:00
wally	Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage.	2021-08-23 15:46:17 -05:00