cvw/wally-pipelined/src
Katherine Parry 85d240c2a5 fpu cleanup
2021-07-24 15:00:56 -04:00
..
cache Removed the hardware page table walker fault state from the icache so that the icache will only unstall CPU for 1 cycle. 2021-07-22 19:42:19 -05:00
ebu moved subwordread to lsu 2021-07-17 20:37:20 -04:00
fpu fpu cleanup 2021-07-24 15:00:56 -04:00
generic renamed or_rows.sv 2021-07-16 20:17:03 -04:00
hazard Renamed DCacheStall to LSUStall in hart and hazard. 2021-07-15 10:16:16 -05:00
ieu Moved the ReadDataW register into the datapath. 2021-07-22 14:52:03 -05:00
ifu Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-21 16:44:32 -05:00
lsu Removed the hardware page table walker fault state from the icache so that the icache will only unstall CPU for 1 cycle. 2021-07-22 19:42:19 -05:00
mmu Cleaned up priority thermometer verilog. passses regression, ideally shortens critical path through pmp's 2021-07-23 11:57:58 -05:00
muldiv Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported 2021-07-04 19:33:46 -04:00
privileged fixed issue with tlbflush remaining high during a stalled sfence instruction 2021-07-21 17:43:36 -04:00
uncore fix UART RX FIFO bug where tail pointer can overtake head pointer 2021-07-22 02:09:41 -04:00
wally Moved the ReadDataW register into the datapath. 2021-07-22 14:52:03 -05:00