Jordan Carlin
5661dc4a03
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
2024-07-18 21:36:00 -07:00
Jordan Carlin
8853fd52bc
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
2024-07-18 21:36:00 -07:00
Rose Thompson
f84aa40b13
Fixed wally.do to correctly log functional coverage.
2024-07-16 15:52:52 -05:00
Rose Thompson
19e9dc5ce0
Fixed wally.do to correctly log functional coverage.
2024-07-16 15:52:52 -05:00
David Harris
fa75077d2f
More attempts at functional coverage
2024-07-15 15:34:44 -07:00
David Harris
d86ef9673d
More attempts at functional coverage
2024-07-15 15:34:44 -07:00
David Harris
2c487935e6
Attempt at functional coverage; breaks code and functional coverage
2024-07-15 14:20:48 -07:00
David Harris
ac05fa5553
Attempt at functional coverage; breaks code and functional coverage
2024-07-15 14:20:48 -07:00
David Harris
04cd2c8ea4
Renamed --coverage to --ccov and moved UCDB files to questa/ucdb
2024-07-15 05:32:16 -07:00
David Harris
467436e30c
Renamed --coverage to --ccov and moved UCDB files to questa/ucdb
2024-07-15 05:32:16 -07:00
Jordan Carlin
2528830e98
Merge remote-tracking branch 'upstream/main' into installation
...
Fix derivgen.pl shebang conflict
2024-07-08 06:46:41 -07:00
Jordan Carlin
09a061b580
Merge remote-tracking branch 'upstream/main' into installation
...
Fix derivgen.pl shebang conflict
2024-07-08 06:46:41 -07:00
David Harris
ced8038343
Defined memory to be inaccessible by default
2024-07-05 08:34:28 -07:00
David Harris
12717a65f2
Fixed location of imperas.ic with new misa_B_Zba_Zbb_Zbs
2024-07-04 12:29:59 -07:00
David Harris
775930ae4f
Fixes to memfile generation for rv32. Updated new misa.B in imperas.ic, but need new version of ImperasDV to test
2024-07-04 07:36:56 -07:00
Jordan Carlin
8991931bef
Update run_vcs shebang after merge
2024-07-03 23:47:26 -07:00
Jordan Carlin
985d9b4edc
Update run_vcs shebang after merge
2024-07-03 23:47:26 -07:00
Jordan Carlin
838e44a53f
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
2024-07-03 23:44:25 -07:00
Jordan Carlin
0459c68615
Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
2024-07-03 23:44:25 -07:00
Jordan Carlin
e5c82e7465
Additional shebang updates
2024-07-03 21:34:48 -07:00
Jordan Carlin
a30d4b29df
Additional shebang updates
2024-07-03 21:34:48 -07:00
Jordan Carlin
e6e070f4e4
Update python shebangs to use /usr/bin/env python3 so virtual environment can be used (also aids in general portability)
2024-07-03 20:42:55 -07:00
Jordan Carlin
7419689359
Update python shebangs to use /usr/bin/env python3 so virtual environment can be used (also aids in general portability)
2024-07-03 20:42:55 -07:00
David Harris
af4403342f
renamed run_vcs.py to run_vcs, added instr/data in ebu
2024-07-03 08:02:38 -07:00
David Harris
1b62d2116a
VCS lockstep working
2024-07-02 18:05:13 -07:00
David Harris
aff0ad9c02
Progress on VCS; run_vcs rewritten in Python to ease passing parameters
2024-07-02 14:23:34 -07:00
David Harris
c972a914c8
Removed +plusarg_save because it doesn't silence VCS
2024-06-28 07:48:01 -07:00
David Harris
4a3532bf5a
VCS lockstep progress
2024-06-28 07:19:03 -07:00
David Harris
6cf250821d
Added VCS +plusarg_save to silence compiler
2024-06-28 06:53:44 -07:00
David Harris
e795143983
Turned off debug access to speed up VCS
2024-06-28 06:43:14 -07:00
David Harris
31b54fb247
Progress on VCS lockstep
2024-06-27 11:16:17 -07:00
Jordan Carlin
b76941d278
Use VCS built-in default macro instead of defining SIM_VCS
2024-06-21 15:17:59 -07:00
Rose Thompson
46ace521c6
Updated verilator makefile.
2024-06-19 16:25:31 -05:00
Ross Thompson
2d8973df1d
Updated wavefile to use new names.
2024-06-19 13:57:28 -07:00
Ross Thompson
64712d2243
Updated wave to match changes in testbench.
2024-06-19 13:51:50 -07:00
Ross Thompson
ab1ee3d69b
Removed *** from IFU, lrcs.
2024-06-19 09:40:35 -07:00
Jordan Carlin
00ccd80479
Update VCS RTL file exclusions with renamed ram
2024-06-18 22:47:00 -07:00
David Harris
bfd3c9fe86
Fixed gettenvval when variable is undefined per verilator Issue 5179
2024-06-14 07:09:53 -07:00
Ross Thompson
563980443a
Merge branch 'main' into rvvi
2024-06-10 18:10:23 -07:00
Rose Thompson
a88d5f403b
Functional coverage works with wally.do
2024-05-28 14:02:54 -05:00
Rose Thompson
0c5b70c40a
It's a bit hacky. But I've got functional coverage working with our wally.do script and testbench.sv.
2024-05-28 13:54:48 -05:00
Rose Thompson
48fd365b9d
Still don't understand why wally.do can't load testbench.sv with functional coverage. But wally-imperas-cov.do can load testbench.sv with functional coverage.
2024-05-28 13:00:17 -05:00
Rose Thompson
4a1e856b18
Almost working functional coverage in wally.do
...
riscvISACOV is now loading, but for some reason I still cannot get it to record anything.
Instead it is just logging the instructions.
2024-05-27 18:15:12 -05:00
Rose Thompson
92ee56c1a1
Yay. Finally found the bug which prevented wally.do from having functional coverage using riscvISACOV.
...
testbench.sv was missing the trace2cov instance.
2024-05-27 17:25:20 -05:00
Rose Thompson
4c0261fd2c
Closer. Needed to reorder includes and defines.
2024-05-27 15:37:16 -05:00
Rose Thompson
ff611016c7
Closer?
2024-05-27 14:11:02 -05:00
Rose Thompson
2985cfb7eb
Preliminary work to merge functional coverage into wally.do.
2024-05-27 11:59:13 -05:00
Rose Thompson
dc09e1c0c5
Modified names so they don't conflict with FPGA's axi signals.
2024-05-24 16:38:47 -05:00
Rose Thompson
1f7d732dca
Moved the rvvisynth code to testbench since I only want this for simulation and fpga.
2024-05-24 16:10:58 -05:00
Rose Thompson
bf9f45d319
We have a simulation of the ethernet transmission working.
...
This commit does not include the source files for the ethernet as it does not belong to cvw.
I'll want to fork that repo and make it a submodule as I need to change the source a bit.
2024-05-24 11:25:42 -05:00
Jordan Carlin
6a2192db6e
Revert "Remove existing derived configs before creating new ones"
2024-05-23 13:56:38 -07:00
Jordan Carlin
fb8e97dd04
Remove existing derived configs before creating new ones
2024-05-23 13:17:24 -07:00
Rose Thompson
b127c19242
Merge branch 'main' into rvvi
2024-05-20 16:31:06 -05:00
Rose Thompson
a885240fbd
temporary commit to help debug merging testbench.sv with testbench-imperas.sv
2024-05-17 12:36:00 -05:00
Rose Thompson
bd8450734b
Fixed more bugs with wally.do.
2024-05-17 10:39:00 -05:00
Rose Thompson
46e6459965
Updated script to run linux with imperasDV.
2024-05-14 13:46:27 -05:00
Rose Thompson
970af9551c
Fixed bug with gui mode testbench_fp
...
removed old wally-linux-imperas.do
2024-05-14 13:41:20 -05:00
Rose Thompson
30bea18dec
Maybe have imperasDV linux simulation merged into wally.do
2024-05-14 12:38:19 -05:00
Rose Thompson
e8f5545076
Got imperasDV running linux simulation again.
...
Now need to merge do files.
2024-05-13 16:43:13 -05:00
Rose Thompson
ceb31fec68
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-10 08:54:23 -05:00
Rose Thompson
b027fa44ef
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-05-10 08:53:00 -05:00
Rose Thompson
93ea5b0c1e
Fixed wavefile to have function logger.
2024-05-10 08:50:42 -05:00
David Harris
04457d49f7
Updated sim-testfloat-verilator to use wsim
2024-05-10 05:03:24 -07:00
David Harris
61e559606e
Fixed wsim to be able to invoke TestFloat with Verilator. However, TestFloat produces incorrect results with Verilator
2024-05-09 18:56:59 -07:00
David Harris
0d1d59a3d8
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-05-08 18:58:01 -07:00
Divya2030
eff2264752
Code Coverage Text format for each test and configuration in IndividualCovReport
2024-05-08 05:24:24 -07:00
Divya2030
b4b88c5858
VCS regression & Code Coverage
2024-05-08 04:39:42 -07:00
Divya2030
31ae18922b
regression_wally vcs run works
2024-05-08 04:25:03 -07:00
David Harris
927f166e1f
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-05-07 12:58:40 -07:00
Divya2030
a3f1a274d2
VCS Simulation Passed
2024-05-07 10:41:02 -07:00
David Harris
37fc45cd35
Updated Questa wally.do to terminate on a compile error
2024-05-06 11:28:00 -07:00
Divya2030
48ad4d6001
pmp coverage
2024-05-02 11:52:54 -07:00
Divya2030
3853f94337
Revert "initial commit pmp basic coverage working"
...
This reverts commit 7ca1c976c0
2024-05-02 11:23:59 -07:00
Divya2030
7ca1c976c0
initial commit pmp basic coverage working
2024-05-02 10:33:29 -07:00
Kunlin Han
cde284d003
Fix the problem of missing sim/verilator/wkdir
2024-04-30 10:48:42 -07:00
David Harris
8f0c68373e
Verilator fulladder example improvmeents
2024-04-28 22:08:00 -07:00
David Harris
1274ec55af
Resolved merge conflict
2024-04-26 16:15:23 -07:00
Quswar Abid
f999ccadf4
/cad/mentor/questa_sim-2023.4/questasim is fixed, relative paths to design and testbench files are fixed, and RISCV-DV submodule is updated back to the latest commit on master branch
2024-04-26 15:55:39 -07:00
David Harris
5d97858806
Moved functional coverage files to sim/questa and to tests/riscvdv
2024-04-24 11:46:38 -07:00
David Harris
5f3676dfd7
Merge pull request #753 from quswarabid/riscvdv_bringup
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RISCVDV bringup - Coverage Collection on RISCVISACOV
2024-04-24 09:47:34 -07:00
Quswar Abid
7b441d2881
Bringup of RISCV-DV to collect functional coverage - Update to track RV64IMAFDC_Zicsr related coverpoints from riscvISACOV
2024-04-23 18:20:29 -07:00
David Harris
0dc2c7d16a
Fixed deriv path in Verilator makefile
2024-04-23 10:19:08 -07:00
David Harris
f9eec8c43f
Merged wsim changes
2024-04-22 13:11:35 -07:00
Kunlin Han
9be0303493
Add support for dumping vcd.
2024-04-22 13:03:51 -07:00
David Harris
cc236bdb25
Resolved merge conflicts
2024-04-22 12:16:06 -07:00
Kunlin Han
c134b712c4
Merge branch 'main' into verilator
2024-04-22 11:35:18 -07:00
Kunlin Han
c383bef1ad
Run verilator configurations and testsuites in different folders.
2024-04-22 11:32:46 -07:00
David Harris
45196a9959
ignore VCS junk files
2024-04-21 19:49:55 -07:00
David Harris
00a1c0fc57
Fixed WALLY/RISCV paths in testbench/rom1p1r; search log files for warnings and errors
2024-04-21 00:02:15 -07:00
David Harris
fd6a6b2249
environment variable cleanup
2024-04-20 22:52:08 -07:00
David Harris
a1876b1e7c
script cleanup
2024-04-20 17:22:31 -07:00
David Harris
571b67f565
Merging PR738
2024-04-20 17:15:17 -07:00
slmnemo
6458fa5642
Merge branch 'main' of https://github.com/openhwgroup/cvw into linux_nightly
2024-04-20 14:46:35 -07:00
David Harris
3cb5cd0cb1
simulator cleanup
2024-04-20 14:12:55 -07:00
David Harris
c8e7a6990d
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-04-20 11:44:27 -07:00
David Harris
bf2f6859e4
Changed Verilog makefile to print transcript to stdout by default like Questa; redirected to logfile elsewhere
2024-04-20 11:27:54 -07:00
David Harris
84e8d86d2a
Merge pull request #739 from Karl-Han/deriv_support
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Add extra path to search for deriv/buildroot
2024-04-20 11:23:54 -07:00
slmnemo
2b0cf90a99
Merged with merge conflict
2024-04-17 10:47:28 -07:00
Kunlin Han
91a88fa46c
Update sim/verilator/Makefile with more comments and merging variables.
2024-04-17 09:52:54 -07:00
Kunlin Han
392eedb342
Update sim/verilator/Makefile with constants for simplicity.
2024-04-16 18:54:11 -07:00
