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Author	SHA1	Message	Date
Rose Thompson	e07f303353	Have basic rv32gc functional coverage running with open source riscvISACOV.	2024-08-29 15:29:04 -07:00
Rose Thompson	dc9a77e45a	Updated riscvISACOV submodule to https instead of ssh.	2024-08-29 14:54:47 -07:00
Rose Thompson	a1c6bc854e	Fixed a subtle questa sim bug with imperasDV. On some linux systems ... vsim will default to 32-bit mode rather than 64-bit, but the ImperasDV libraries are 64-bit. vsim must run in 64-bit mode.	2024-08-29 14:00:52 -07:00
Rose Thompson	0ce4d1b452	Merge branch 'main' of github.com:openhwgroup/cvw	2024-08-29 10:50:27 -07:00
Rose Thompson	6ad2c2e7a6	Merge pull request #935 from davidharrishmc/dev ... Added lockstep support for RV32. Not all wally privileged tests pass…	2024-08-29 10:45:17 -07:00
David Harris	26f3c2a607	Added lockstep support for RV32. Not all wally privileged tests pass yet	2024-08-29 10:44:37 -07:00
David Harris	ca4dcfdaa9	Merge pull request #934 from JacobPease/main ... Custom test spitest fix	2024-08-28 02:13:06 -07:00
Jacob Pease	c4d909c412	Merge branch 'main' of github.com:openhwgroup/cvw	2024-08-28 04:10:38 -05:00
Jacob Pease	3b91977227	Added start.s to spitest directory.	2024-08-28 04:10:24 -05:00
Rose Thompson	cb05697698	Added basic SPI signals to waveform.	2024-08-27 15:51:19 -07:00
Rose Thompson	7e16ddd859	Improved fpga synth script.	2024-08-27 15:50:05 -07:00
Rose Thompson	e5d3462a90	Converted wall.tcl to entirely project mode.	2024-08-27 14:15:58 -07:00
Rose Thompson	0ce289c937	Merge pull request #933 from JacobPease/main ... Committing the custom test spitest.	2024-08-27 12:43:19 -07:00
Jacob Pease	44ece7cb96	Added CVW header to spitest files.	2024-08-27 14:28:49 -05:00
Jacob Pease	b7a74307c5	Committing the custom test spitest.	2024-08-27 14:19:56 -05:00
Rose Thompson	2dd897e7e1	Merge pull request #932 from davidharrishmc/dev ... Added temporary --fcov2 option to start adopting open-source riscvISACOV	2024-08-27 08:47:59 -07:00
David Harris	9df38e14b2	Added temporary --fcov2 option to start adopting open-source riscvISACOV	2024-08-27 08:40:44 -07:00
Rose Thompson	f20a1564fa	Added SPI debugger.	2024-08-26 17:22:13 -07:00
Rose Thompson	f31eb62c1b	Merge pull request #929 from JacobPease/main ... Bootloader Speed Improvements	2024-08-26 09:10:42 -07:00
Jordan Carlin	99da7e7b21	Merge pull request #931 from davidharrishmc/dev ... Fixed imperas configuration and updated files for new Imperas/Synopsy…	2024-08-25 14:55:42 -07:00
David Harris	30694f4ed0	Fixed imperas configuration and updated files for new Imperas/Synopsys licenses	2024-08-25 14:46:22 -07:00
Jacob Pease	d649473ec8	Merge branch 'main' of github.com:openhwgroup/cvw	2024-08-24 21:57:44 -05:00
Jacob Pease	ad6734eb6d	Improved the speed of the bootloader by 60s. CRC16 is now calculated with a table and a byte is now sent for every byte read, keeping the FIFO full.	2024-08-24 21:36:29 -05:00
David Harris	86aaf43306	Merge pull request #928 from ross144/main ... Update FPGA constraints to restore support for VCU108 and increase speed to 50MHz	2024-08-24 18:45:55 -07:00
Rose Thompson	ea181a2ba3	Merge branch 'main' of github.com:openhwgroup/cvw	2024-08-23 17:37:14 -07:00
Rose Thompson	ee1e09a6a2	VCU108 now boot linux at 50MHz!	2024-08-23 17:18:47 -07:00
Rose Thompson	14083bc642	VCU108 is not synthesizing at 50MHz. Still running into a few problems ... with the new SPI sd card device.	2024-08-23 16:17:15 -07:00
Rose Thompson	842aea157c	Updated vc108 constraints for spi based sd card and setting 50 Mhz.	2024-08-23 15:59:11 -07:00
Rose Thompson	167878aee4	Commet out debug code in fpga synth script.	2024-08-23 14:46:01 -07:00
Rose Thompson	b471913d9f	On the way to making vcu108 work again.	2024-08-23 14:45:22 -07:00
Rose Thompson	4d56b3ca96	Maybe improvements to fpga synthesis.	2024-08-23 13:00:22 -07:00
David Harris	aba4caa108	Merge pull request #927 from 10x-Engineers/rvvi_setup ... Removing warnings from questa simulation	2024-08-23 06:34:35 -07:00
Huda-10xe	da2c9a5dc5	Removing warnings from questa simulation	2024-08-23 12:37:42 +05:00
Rose Thompson	fc80bf1251	More updates to fpga IP module names.	2024-08-22 14:31:39 -07:00
Rose Thompson	8d40a0a092	Changed names of fpga IP modules to match textbook. Updated boot.h to ... use the correct clock speed for #DEFINE for UART in the zero stage bootloader.	2024-08-22 13:56:50 -07:00
David Harris	b4bcd7b0b1	Merge pull request #926 from ross144/main ... Fix my name on multiple files and other minor changes	2024-08-22 03:23:17 -07:00
Rose Thompson	418bc6b23c	Merge branch 'main' of github.com:openhwgroup/cvw	2024-08-21 16:24:10 -07:00
Rose Thompson	1f57fd6343	Fixed bug in Makefile.	2024-08-21 16:04:21 -07:00
Rose Thompson	249db9cf45	Merge pull request #925 from JacobPease/main ... Update PREADY signal to not stall during transmission on reads to read only registers.	2024-08-21 12:44:57 -07:00
Rose Thompson	f5d754d2a5	Updated to point to latest commit of cvw-arch-verif.	2024-08-21 11:02:23 -07:00
Rose Thompson	6be30369f1	Merge branch 'main' of github.com:openhwgroup/cvw	2024-08-21 11:02:23 -07:00
Rose Thompson	faffecf891	Merge branch 'main' of github.com:openhwgroup/cvw	2024-08-21 11:02:17 -07:00
Rose Thompson	01b623b8c4	Merge branch 'main' of github.com:openhwgroup/cvw	2024-08-21 11:02:08 -07:00
Rose Thompson	ae8c2f26c6	Fixed wave file to add back the function name.	2024-08-21 10:51:32 -07:00
Rose Thompson	113d71f1a0	More name updates.	2024-08-21 10:51:24 -07:00
Rose Thompson	f603d21826	Updated my name in multiple locations.	2024-08-21 10:50:39 -07:00
Jacob Pease	938879c5a4	Update PREADY signal to not stall during transmission on reads to read only registers.	2024-08-21 12:39:01 -05:00
David Harris	6f19ad554f	Merge pull request #923 from 10x-Engineers/rvvi_setup ... Adding regression for RVVI FC	2024-08-21 05:22:38 -07:00
David Harris	67c7a559c3	Merge pull request #923 from 10x-Engineers/rvvi_setup ... Adding regression for RVVI FC	2024-08-21 05:22:38 -07:00
Huda-10xe	b315a8e338	Adding regression commands to Makefile	2024-08-21 15:45:23 +05:00