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348 Commits

Author SHA1 Message Date
Rose Thompson
faea7db1b2 Reverted linux testbench to not check for match against QEMU. 2023-10-17 10:00:50 -05:00
naichewa
0ff9ce527d Merge branch 'main' into spi 2023-10-16 22:59:50 -07:00
naichewa
4941fe1769 sync fifo passes 2023-10-16 22:57:02 -07:00
David Harris
fab9fbd7f1 Merged testbench 2023-10-16 13:52:24 -07:00
David Harris
1a6e57f8c0 Renamed wally-config to config in many comments 2023-10-16 13:49:09 -07:00
David Harris
ac4216b43d Incorporated new AMO tests from riscv-arch-test 2023-10-16 10:25:45 -07:00
Rose Thompson
8f2ca2ae15 Added missing files. 2023-10-13 15:10:58 -05:00
Rose Thompson
8d4cdcbd1a Renamed testbench_imperas.sv to testbench-imperas.sv 2023-10-13 14:56:45 -05:00
Rose Thompson
c1d6fddea8 Removed P.FPGA from testbench. 2023-10-13 14:08:17 -05:00
naichewa
d5d4f9d044 transferred spi changes in ECA-authorized commit 2023-10-12 13:36:57 -07:00
Lee Moore
0a0d6dd25e Merge branch 'openhwgroup:main' into main 2023-10-06 11:46:45 +01:00
Ross Thompson
fc83f33615 Oups. When fixing the linux-imperasdv testbench I accidentally introduced a bug to the tracer. 2023-10-05 13:00:46 -05:00
Ross Thompson
824f37bba4 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-10-05 10:39:06 -05:00
Ross Thompson
81c44a4cb3 Fixed imperas linux testbench. 2023-10-04 17:11:47 -05:00
David Harris
28752303be Added ZCA/ZCF/ZCD/ZCB support. Doesn't break regression, but not tested. Need to get tests for Zcb. Draft tests are in riscv-arch-test but not yet committed there 2023-10-04 12:28:12 -07:00
James E. Stine
58e7be2338 Fix testfloat testbench to work properly with parameters 2023-10-03 08:11:45 -05:00
eroom1966
381cfdcb4b bring upto date with latest IDV 2023-09-21 11:29:31 +01:00
Ross Thompson
271c7e43ab Merge pull request #403 from davidharrishmc/dev 
Initial TLB NAPOT tests
 2023-08-29 16:43:35 -05:00
David Harris
91429f3f02 Initial TLB NAPOT tests 2023-08-29 12:39:24 -07:00
Ross Thompson
ac0b1fbdb7 Fixed testbench_imperas.sv 2023-08-29 09:01:35 -05:00
David Harris
8d3ff59673 Completed basic tests of svnapot and svpbmt 2023-08-28 06:57:35 -07:00
David Harris
7a092a2275 Fixed merge conflict for ZICBOP 2023-08-25 18:41:57 -07:00
David Harris
c6631ef808 Added N and PBMT bits to MMU PTE 2023-08-24 19:44:46 -07:00
Ross Thompson
cd3349bd26 Added rv32 cboz test. 2023-08-24 17:02:53 -05:00
Ross Thompson
00e65c4ae7 Oups there was a bug in the SATP fix. RV32GC was broken by the changes. 2023-08-23 09:42:46 -05:00
David Harris
d801916d97 Merge pull request #383 from ross144/main 
Adds Zicbom support for D-cache only.  I-cache not yet supported.  Tests 32 and 64 bit versions.  Please rebuild regressions wally32 and wally64.  To save rebuild time edit lines 11-12 of tests/riscof/Makefile
 2023-08-21 13:32:00 -07:00
Ross Thompson
310b700550 Have a working 32 bit cbom test! 2023-08-21 13:46:09 -05:00
Ross Thompson
d4c6ba627d Working CBO tests for 64 bit! 2023-08-21 12:55:07 -05:00
David Harris
2738423441 Improved CSRU coverage with priv.S 2023-08-20 12:49:31 -07:00
Ross Thompson
a89a1e675c Merge branch 'boot' into mergeBoot 
Merges Jacob's new sdc controller into wally.
 2023-07-21 17:43:45 -05:00
Ross Thompson
e4d6a9f8c6 Removed all old configuration files. 2023-07-19 10:28:54 -05:00
Ross Thompson
b756b248b4 Wow. The newest version of Vivado does not like the enums as parameters. 
The solution is simple.  I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
 2023-07-18 15:07:10 -05:00
Ross Thompson
59022099c7 Fixed the icache and dcache overlogging issue. 2023-07-14 15:47:05 -05:00
Ross Thompson
33d8e5687e Merge branch 'main' of github.com:ross144/cvw 2023-07-11 15:09:07 -05:00
Ross Thompson
99073a70c0 Added wfi and interrupt to tracer. 2023-07-11 15:09:04 -05:00
Ross Thompson
625192d9a4 Merge branch 'main' of github.com:ross144/cvw into main 2023-07-11 15:08:26 -05:00
Ross Thompson
38f32805ae Created separate temporary testbench for xcelium. 2023-07-11 15:07:33 -05:00
Ross Thompson
4653f8e704 Simplificaiton of function tracker. 2023-07-11 10:51:17 -05:00
Ross Thompson
27f6f00402 Changes for xcelium. 2023-07-07 18:22:28 -05:00
Ross Thompson
9a49ec0b98 Removed duplicate signal name from testbench. 2023-07-07 16:34:08 -05:00
Ross Thompson
2ce8b66574 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-06 14:55:43 -05:00
David Harris
b04763bcf2 Commented SVADU requirements for wally32priv mmu tests 2023-07-04 11:34:07 -07:00
David Harris
001d3cfdc5 Added logic to warn about x in memory reads. Added cbo instruction names to testbench decoder 2023-07-02 13:29:27 -07:00
James E. Stine
48bec40902 Modification (temporary) to testbench-fp.sv to allow testing of anything FMA. This might need to be changed with OpCtrl to make more robust for future expansion. 2023-06-29 08:46:11 -05:00
James E. Stine
3cfec29cc7 Minor tweak to fix vectors not working for fadd. 2023-06-26 14:25:44 -05:00
James E. Stine
786329b11d Fix items related to testing of TestFloat that were not always matching. The issue resulted due to the repeat statement that interferes with the always block. I separated the two to allow them to work correctly 2023-06-26 10:14:49 -05:00
James E. Stine
97b1c01dc0 Modify testbench-fp.sv to handle parameterization as well some other minor mods. Have to make a better FPUActive desgination but for now works 2023-06-22 15:27:17 -05:00
James E. Stine
66643eb78e Update sim-testfloat to fix errors due to bad config element. I am not sure of the reasoning, but the specific path to the testvector was not getting inserted in Questa. This modification also adds features to test individualized tests (.e.g, binary16 only) -- documentation is added in the FPbuild.txt file 2023-06-20 17:26:54 -05:00
Ross Thompson
a8f11dcad0 FPGA updates. 2023-06-20 11:11:34 -05:00
Ross Thompson
f5cee3fb66 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-18 16:37:19 -05:00
David Harris
5d6eb40c2d Fixed embench to run all tests, even ones not in 1.0 2023-06-17 20:38:51 -07:00
David Harris
2db94e7ddd Replaced zext.h with zext.h_64 in rv64 tests because old one is obsolete 2023-06-16 16:07:28 -07:00
Ross Thompson
443c568994 Vivado requires an intermediate wrapper file for parameterization. 2023-06-16 16:30:14 -05:00
David Harris
b1bfba7995 erge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-06-16 10:32:37 -07:00
David Harris
ea1f731cd5 Merge pull request #342 from ross144/main 
Testbench generates embench output files
 2023-06-16 10:32:18 -07:00
Ross Thompson
7f79c0a855 Modified the testbench to generate the required files for embench scripts. 2023-06-16 12:27:22 -05:00
David Harris
924a3ea3cf Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-06-16 10:03:48 -07:00
David Harris
ba2ee7453b Merge pull request #341 from ross144/main 
Fix embench so it does not crash
 2023-06-16 10:03:41 -07:00
Ross Thompson
4d76e83318 embench testbench no longer crashes. 2023-06-16 11:54:41 -05:00
David Harris
c2913f49a3 Added assertions for ZICNTR and ZIHPM 2023-06-16 09:26:02 -07:00
eroom1966
5f358d1af7 add changes for latest IDV file layout 2023-06-16 16:43:53 +01:00
Ross Thompson
d46500bfe0 Fixed the imperas testbench to work with parameters. 2023-06-16 08:59:52 -05:00
Ross Thompson
f3d35f914a Have the linux testbench working in the mean time. Before the consolidation. 2023-06-15 16:18:37 -05:00
Ross Thompson
4428babda9 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 15:38:38 -05:00
Ross Thompson
85567841eb Merge branch 'testbench-params2' 2023-06-15 15:31:13 -05:00
Ross Thompson
d2219023c3 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 14:57:23 -05:00
Ross Thompson
af046d4772 Major cleanup of testbench. 2023-06-15 14:57:05 -05:00
Ross Thompson
75b5c23edd Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems. 2023-06-15 14:05:44 -05:00
Ross Thompson
b8a243827b Found a whole bunch of files still using the old `define configurations. 2023-06-15 13:09:07 -05:00
David Harris
45ee4c2f9f Added BMU instructions to instruction name decoder 2023-06-15 09:26:09 -07:00
Ross Thompson
301d54fea8 Significant refactoring of testbench. 2023-06-14 17:02:49 -05:00
Ross Thompson
4d2bb0ea83 Removed old configs from function name module. 2023-06-14 16:35:55 -05:00
Ross Thompson
8f09e17dc7 Found and fixed the source of the new testbench slow down. I accidentally increased the size of the signature buffer by 10x. 2023-06-14 14:11:25 -05:00
Ross Thompson
6330e8084c more testbench improvements. 2023-06-14 12:23:26 -05:00
Ross Thompson
6e42b9f865 Continued improvements to testbench. 2023-06-14 12:11:55 -05:00
Ross Thompson
10c6c08136 Resolved the duplicated check signature issue. 2023-06-14 11:50:12 -05:00
Ross Thompson
3a78d4ca73 Fixed another issue with the timing of memory resets in the new testbench. 2023-06-13 16:24:38 -05:00
Ross Thompson
af8ca85a5b Now have most of the regression tests running again. 2023-06-13 15:09:40 -05:00
Ross Thompson
836bc4a4f7 Cleaned up testbench more. 2023-06-13 14:05:17 -05:00
Ross Thompson
4bdecf8c6d Compacted memory resets. 2023-06-13 13:57:58 -05:00
Ross Thompson
91a22c3a8a More cleanup. 2023-06-13 13:54:07 -05:00
Ross Thompson
9869b26556 Fixed the multliple reads of the same preload memory file. 2023-06-13 13:52:02 -05:00
Ross Thompson
df62f3964c The testbench now at least runs the arch64i in rv64gc config. Still has several issues 
1. need to remove all dead code
2. seems to still be double reading memory files sometimes.
3. batch mode does not work.
 2023-06-13 13:18:46 -05:00
David Harris
004aeda362 Revert "Update for new layout of ImperasDV files" 2023-06-13 04:17:56 -07:00
Ross Thompson
fe72264de3 The new testbench is almost working except the shadow copy is not working. 2023-06-12 15:08:23 -05:00
Ross Thompson
9eeac21113 Progress towards new testbench. 2023-06-12 14:06:17 -05:00
Ross Thompson
3ef2031791 Created temporary wrapper for lint. 2023-06-12 11:49:51 -05:00
Ross Thompson
ee4352975c This parameterizes the testbench but does not use the verilator updates or the new testbench. 2023-06-12 11:00:30 -05:00
eroom1966
d61ed17730 Update for new layout of ImperasDV files 2023-06-12 09:29:07 +01:00
Ross Thompson
8d1dee5764 Removed comments around commented code for verilator. 2023-06-11 15:30:51 -05:00
Ross Thompson
e27dfb8ce0 Merge branch 'verilator' 2023-06-11 15:28:04 -05:00
James E. Stine
67d21ae3a6 Update testbench-fp thanks to Kevin's help - also fixed add which was broken due to config 2023-06-11 15:15:47 -05:00
David Harris
f68b9c224a Fixed WALLY-trap test case to use menvcfg 2023-06-09 15:24:26 -07:00
Ross Thompson
39c8f11191 Fixed the garbled output in embench transcript. 2023-06-08 10:43:46 -05:00
Ross Thompson
4ddbbd6948 Merge pull request #314 from davidharrishmc/dev 
Make and FP script improvements
 2023-06-06 12:38:26 -04:00
Ross Thompson
918464c236 Found the coremark performance issue. The testbench was continuously forcing the BTB to all zeros. Once fixed it resolved the performance problem. 2023-06-05 15:42:05 -05:00
Ross Thompson
1ceea51d8b Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet. 2023-05-31 16:51:00 -05:00
David Harris
65dd99af0c Support all testfloat tests with parameterized design 2023-05-31 06:30:21 -07:00
Ross Thompson
8648d0c25c Hacked it together, but I think testfloat is working. 2023-05-30 15:51:13 -05:00
Ross Thompson
04d0fd94f0 Merge branch 'param-lim-merge' 2023-05-26 16:25:35 -05:00
Ross Thompson
88cc473c68 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-05-24 13:00:50 -05:00
Ross Thompson
930fb67308 Trying to figure out why the parameterization slowed down modelsim so much. 2023-05-24 12:44:42 -05:00
Ross Thompson
2ddb8c7c78 Merge pull request #297 from davidharrishmc/dev 
Verilator testbench changes
 2023-05-22 13:29:54 -04:00
David Harris
163b05f1ce Removed force from branch predictor initialization 2023-05-22 09:57:41 -07:00
David Harris
84dac82def Initial testbench cleanup for Verilator 2023-05-22 09:51:46 -07:00
Ross Thompson
664231c0da Merge branch 'localhistory' 
Repair to wave file.
Created implementations of local history. Part of my Ph.D. research.
 2023-05-22 10:13:31 -05:00
David Harris
7b0d1a7883 Factored FMA tests out of the main 32/64 f/d tests to run in parallel and speed up sim 2023-05-16 11:37:01 -07:00
Ross Thompson
3a98fb8680 Baseline localhistory with speculative repair built. 2023-05-05 15:23:45 -05:00
Ross Thompson
8b0791b6b5 I think ahead pipelining is working for local history. 2023-05-03 12:52:32 -05:00
Ross Thompson
0904a9b97f Swapped the m and k parameters for local history predictor. 2023-05-02 10:52:41 -05:00
Kevin Wan
9ca738547e fixed tests.vh test lines 2023-04-28 07:47:59 -07:00
Kevin Wan
39c9cd5ee9 added tests for pmppriority module 2023-04-27 16:12:43 -07:00
Noah Limpert
4ec31de316 complete camline coverage on IFU and LSU 2023-04-27 14:26:10 -07:00
Noah Limpert
a0e71c26cb Add in a test that makes match 3 = 0 for all tlb lines 2023-04-20 14:50:06 -07:00
Noah Limpert
7ca44de126 Commiting changes to add coverage to ASID, Global, Megapage size checks. 2023-04-20 14:38:13 -07:00
David Harris
6e612a1693 Update tests.vh 
Missing comma from merge
 2023-04-19 06:23:05 -07:00
David Harris
4cbffd7972 Merge branch 'main' into coverage4 2023-04-19 06:16:07 -07:00
David Harris
b63dff098a Merge branch 'main' into main 2023-04-19 04:50:12 -07:00
David Harris
156a098884 Merge branch 'main' into main 2023-04-19 04:46:51 -07:00
Alec Vercruysse
b3a3af8ed3 add D$ test case to trigger a FlushStage while SetDirtyWay=1 
This hits some conditional coverage in each cacheway.
A cache store hit happens at the same time as a StoreAmoMisalignedFault.
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
cd803bfa44 Cover CacheWay edge case: CacheDataMem we=1 while ce=0. 
This test basically triggers an i$ miss during a d$ (hit) store
operation. It requires some tricky timing (e.g. a flushD right
before the relevant store). I use a script to generate the test.
 2023-04-19 01:34:01 -07:00
Liam
9b72d6ac37 Update tests.vh 2023-04-18 23:15:47 -07:00
Kevin Wan
771124e265 Completely covers all PMPCFG_ARRAY_REGW cases 2023-04-18 21:50:48 -07:00
Kevin Wan
1bdae2285d PMPCFG_ARRAY_REGW cases 2023-04-18 18:43:50 -07:00
Kevin Thomas
db0ca8695a Add PR#252 test file to coverage 2023-04-18 17:57:56 -05:00
Limnanthes Serafini
2d9de7b58f Merge branch 'openhwgroup:main' into code_quality 2023-04-13 19:59:58 -07:00
Limnanthes Serafini
ff72cbc1b2 Finished up testbench reformatting 2023-04-13 19:18:26 -07:00
Limnanthes Serafini
b9c97c6a8c Further indents 2023-04-13 19:07:43 -07:00
Limnanthes Serafini
44356559bc testbench code visual improvements 2023-04-13 19:06:09 -07:00
David Harris
17ecb0103e Merge pull request #243 from Noah-G-L/main 
Pull Request to add tlbKP.S - Fill in cache lines
 2023-04-13 18:13:04 -07:00
Limnanthes Serafini
2e809a4e69 A couple indents->spaces 2023-04-13 17:00:41 -07:00
Noah Limpert
d1cb3ca013 git did not seem to add tests.vh, trying again 2023-04-13 16:59:10 -07:00
Limnanthes Serafini
95586abe09 Merge branch 'cachesim' of https://github.com/AlecVercruysse/cvw into cachesim 2023-04-13 16:54:16 -07:00
Limnanthes Serafini
7d274eae74 Fix of InvalDelayed warning 2023-04-13 16:53:36 -07:00
Ross Thompson
10be07857c Merge pull request #229 from davidharrishmc/dev 
Turned on SVADU_SUPPORTED in rv32/64gc wally-config and in imperas.ic…
 2023-04-12 12:21:03 -05:00
David Harris
e6cb928ab2 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-12 02:57:33 -07:00
David Harris
bedb3f95eb Swapped in svadu mmu tests 2023-04-12 02:06:52 -07:00
Limnanthes Serafini
65d29306ef Merge branch 'openhwgroup:main' into cachesim 2023-04-12 01:34:45 -07:00
James Stine
811004ef9f Update testbench-fp to run TestFloat for all FP operations 2023-04-11 22:16:20 -05:00
Limnanthes Serafini
a6545a0f47 Logger significantly improved. 2023-04-11 19:29:51 -07:00
Kevin Box
59e7c9371a Create new pmp tests 
configures all pmpcfg registers in each different address range.
 2023-04-09 16:29:57 -07:00
David Harris
b27199e276 Added vm64check tests to cover IMMU vm64 2023-04-07 21:14:52 -07:00
eroom1966
47999784d6 fix break to simulation testbench 2023-04-06 14:45:41 +01:00
Ross Thompson
7cdd12a40a Merge pull request #206 from AlecVercruysse/coverage2 
i$ coverage improvements
 2023-04-05 17:29:35 -05:00
Alec Vercruysse
8b6b96012d add ram1p1rwe for read-only cache ways (remove byte-enable) 
- increases coverage
 2023-04-05 11:48:18 -07:00
Limnanthes Serafini
9cbc2a8e4c Merge remote-tracking branch 'upstream/main' into cachesim 2023-04-05 09:53:05 -07:00
David Harris
7c71c21810 Merge pull request #201 from ross144/main 
Improved d/i cache loggers
 2023-04-05 06:40:14 -07:00
Limnanthes Serafini
49226a1eb2 Commenting, attribution for sim, minor log changes 2023-04-05 02:43:02 -07:00
Limnanthes Serafini
53cff56a97 Changed logging enables, debug mode in sim. 2023-04-04 23:49:35 -07:00
Limnanthes Serafini
6f7620e7c1 CacheSim edits, tests. I/D$ logging, Lim's version 2023-04-04 21:12:35 -07:00