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Commenting, attribution for sim, minor log changes
This commit is contained in:
Limnanthes Serafini
parent
0aadbd8492
commit
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@ -1,15 +1,46 @@
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#!/usr/bin/env python3
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# Authors: Limnanthes Serafini (lserafini@hmc.edu) and Alec Vercruysse (avercruysse@hmc.edu)
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# TODO: add better (more formal?) attribution, commenting, improve output
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###########################################
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## testcount.pl
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##
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## Written: lserafini@hmc.edu
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## Created: 27 March 2023
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## Modified: 5 April 2023
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##
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## Purpose: Simulate a L1 D$ or I$ for comparison with Wally
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##
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## A component of the CORE-V-WALLY configurable RISC-V project.
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##
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## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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##
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## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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##
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## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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## except in compliance with the License, or, at your option, the Apache License version 2.0. You
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## may obtain a copy of the License at
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##
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## https:##solderpad.org/licenses/SHL-2.1/
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##
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## Unless required by applicable law or agreed to in writing, any work distributed under the
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## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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## either express or implied. See the License for the specific language governing permissions
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## and limitations under the License.
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################################################################################################
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# how to invoke this simulator:
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# CacheSim.py <number of lines> <number of ways> <length of physical address> <length of tag> -f <log file> (-v)
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# so the default invocation for rv64gc is 'CacheSim.py 64 4 56 44 -f <log file>'
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# the log files to run this simulator on can be generated from testbench.sv
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# by setting I_CACHE_ADDR_LOGGER and/or D_CACHE_ADDR_LOGGER to 1 before running tests.
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# I (Lim) recommend logging a single set of tests (such as wally64priv) at a time.
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# with verbose mode off, the simulator only reports mismatches between its and Wally's behavior.
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# with verbose mode on, the simulator logs each access into the cache.
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import sys
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import math
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import argparse
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import os
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fulltrace = False
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class CacheLine:
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def __init__(self):
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self.tag = 0
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@ -44,21 +75,25 @@ class Cache:
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for i in range(self.numsets):
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self.pLRU.append([0]*(self.numways-1))
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# flushes the cache by setting all dirty bits to False
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def flush(self):
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for way in self.ways:
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for line in way:
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line.dirty = False
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# invalidates the cache by setting all valid bits to False
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def invalidate(self):
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for way in self.ways:
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for line in way:
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line.valid = False
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# resets the pLRU to a fresh 2-D array of 0s
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def clear_pLRU(self):
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self.pLRU = []
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for i in range(self.numsets):
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self.pLRU.append([0]*(self.numways-1))
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# splits the given address into tag, set, and offset
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def splitaddr(self, addr):
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# no need for offset in the sim, but it's here for debug
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tag = addr >> (self.setlen + self.offsetlen) & int('1'*self.taglen, 2)
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@ -66,6 +101,9 @@ class Cache:
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offset = addr & int('1'*self.offsetlen, 2)
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return tag, setnum, offset
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# performs a cache access with the given address.
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# returns a character representing the outcome:
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# H/M/E/D - hit, miss, eviction, or eviction with writeback
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def cacheaccess(self, addr, write=False):
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tag, setnum, _ = self.splitaddr(addr)
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@ -73,8 +111,7 @@ class Cache:
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for waynum in range(self.numways):
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line = self.ways[waynum][setnum]
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if line.tag == tag and line.valid:
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if write:
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line.dirty = True
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line.dirty = line.dirty or write
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self.update_pLRU(waynum, setnum)
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return 'H'
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@ -85,10 +122,7 @@ class Cache:
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if not line.valid:
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line.tag = tag
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line.valid = True
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if write:
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line.dirty = True
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else:
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line.dirty = False
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line.dirty = write
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self.update_pLRU(waynum, setnum)
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return 'M'
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@ -96,17 +130,14 @@ class Cache:
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victim = self.getvictimway(setnum)
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line = self.ways[victim][setnum]
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prevdirty = line.dirty
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#print("Evicting tag", line.tag, "from set", setnum, "way", victim)
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#print("replacing with", tag)
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line.tag = tag
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line.valid = True # technically redundant
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if write:
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line.dirty = True
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else:
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line.dirty = False
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line.dirty = write
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self.update_pLRU(victim, setnum)
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return 'D' if prevdirty else 'E'
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# updates the psuedo-LRU tree for the given set
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# with an access to the given way
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def update_pLRU(self, waynum, setnum):
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if self.numways == 1:
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return
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@ -115,13 +146,14 @@ class Cache:
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bottomrow = (self.numways - 1)//2
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index = (waynum // 2) + bottomrow
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tree[index] = int(not (waynum % 2))
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#print("changing index", index, "to", int(not (waynum % 2)))
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while index > 0:
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parent = (index-1) // 2
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tree[parent] = index % 2
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#print("changing index", parent, "to", index%2)
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index = parent
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# uses the psuedo-LRU tree to select
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# a victim way from the given set
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# returns the victim way as an integer
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def getvictimway(self, setnum):
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if self.numways == 1:
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return 0
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@ -163,12 +195,12 @@ if __name__ == "__main__":
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parser.add_argument('addrlen', type=int, help="Length of the address in bits (a power of 2)", metavar="A")
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parser.add_argument('taglen', type=int, help="Length of the tag in bits", metavar="T")
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parser.add_argument('-f', "--file", required=True, help="Log file to simulate from")
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parser.add_argument('-v', "--verbose", action='store_true', help="verbose/full-trace mode")
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args = parser.parse_args()
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cache = Cache(args.numlines, args.numways, args.addrlen, args.taglen)
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#numtests = -1
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extfile = os.path.expanduser(args.file)
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with open(extfile, "r") as f:
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for ln in f:
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ln = ln.strip()
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@ -179,26 +211,28 @@ if __name__ == "__main__":
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# trying TRAIN clears instead
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cache.invalidate() # a new test is starting, so 'empty' the cache
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cache.clear_pLRU()
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if fulltrace:
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#numtests +=1
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if args.verbose:
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print("New Test")
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else:
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if lninfo[1] == 'F':
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cache.flush()
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if fulltrace:
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if args.verbose:
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print("F")
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elif lninfo[1] == 'I':
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cache.invalidate()
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if fulltrace:
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if args.verbose:
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print("I")
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else:
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addr = int(lninfo[0], 16)
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iswrite = lninfo[1] == 'W' or lninfo[1] == 'A'
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result = cache.cacheaccess(addr, iswrite)
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if fulltrace:
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if args.verbose:
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tag, setnum, offset = cache.splitaddr(addr)
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print(hex(addr), hex(tag), hex(setnum), hex(offset), lninfo[2], result)
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if not result == lninfo[2]:
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print("Result mismatch at address", lninfo[0], ". Wally:", lninfo[2],", Sim:", result)
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print("Result mismatch at address", lninfo[0], ". Wally:", lninfo[2],", Sim:", result) #, "in test", numtests)
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@ -30,8 +30,8 @@
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`define PrintHPMCounters 0
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`define BPRED_LOGGER 0
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`define I_CACHE_ADDR_LOGGER 1
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`define D_CACHE_ADDR_LOGGER 1
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`define I_CACHE_ADDR_LOGGER 0
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`define D_CACHE_ADDR_LOGGER 0
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module testbench;
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parameter DEBUG=0;
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@ -562,11 +562,9 @@ if (`ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin : ICacheLogger
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logic Enable;
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// assign Enable = ~dut.core.StallD & ~dut.core.FlushD & dut.core.ifu.bus.icache.CacheRWF[1] & ~reset;
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// this version of enable does create repeated instructions (i.e, when there's a stall)
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// but! it allows us to correctly log evictions
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// and re-accessing the same portion of memory just generates another hit, so the duplicates are OK
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// for now at least
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assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn;
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// this version of Enable allows for accurate eviction logging.
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// Likely needs further improvement.
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assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn & ~reset;
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flop #(1) ResetDReg(clk, reset, resetD);
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assign resetEdge = ~reset & resetD;
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initial begin
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@ -588,7 +586,7 @@ if (`ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin : ICacheLogger
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end
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end
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// old version
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if (`DCACHE_SUPPORTED && `D_CACHE_ADDR_LOGGER) begin : DCacheLogger
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int file;
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string LogFile;
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@ -610,11 +608,11 @@ if (`ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin : ICacheLogger
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// ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage &
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// (AccessTypeString != "NULL");
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// this version of enable does create repeated instructions (i.e, when there's a stall)
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// but! it allows us to correctly log evictions
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// and re-accessing the same portion of memory just generates another hit, so the duplicates are OK
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// for now at least
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assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn;
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// This version of enable allows for accurate eviction logging.
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// Likely needs further improvement.
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assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn &
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~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage &
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(AccessTypeString != "NULL");
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initial begin
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LogFile = $psprintf("DCache.log");
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