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1629 Commits

Author SHA1 Message Date
Rose Thompson
2f04e5e597 Merge branch 'main' of github.com:rosethompson/cvw 2024-11-25 15:53:27 -06:00
Rose Thompson
7358c1fe67 Fixed sublte bug in the spi_fifo which allows for spurious write to fifo. Fixed fpga zsbl so that is uses read fifo interrupt pending (IP) rather than transmit fifo IP. Resolves issue with stalled load reading the wrong fifo status. 2024-11-25 15:50:29 -06:00
David Harris
ce7b036b78
Merge pull request #1109 from jordancarlin/lint 
More lint cleanup: remove unused params
 2024-11-16 16:34:15 -08:00
Jordan Carlin
f6b0805fd4
More lint cleanup: remove unused params 2024-11-16 12:35:37 -08:00
David Harris
56cbcf222b
Merge pull request #1107 from jordancarlin/lint 
Clean up verilator lint off commands and remove unnecessay ones
 2024-11-16 12:16:52 -08:00
Jordan Carlin
a462b9a2e6
Clean up verilator lint off commands and remove unnecessay ones 2024-11-15 23:52:50 -08:00
David Harris
234e47a7c5 MTIMECMP should reset to maximum value for RV32, not just for RV64 2024-11-15 15:37:25 -08:00
Vikram Krishna
0c0949e82b added explanation 2024-11-14 03:54:32 -08:00
Vikram Krishna
eb777d3fa4 updated froundnx conditional 2024-11-14 03:53:26 -08:00
Vikram Krishna
4aecba2a51 added handling for OpCode=100 2024-11-14 03:51:27 -08:00
Rose Thompson
e22f30ec14 Better name for CacheSetTag2. 2024-11-13 12:24:35 -06:00
Rose Thompson
ef7072b7c2 Merge branch 'main' into lrufixes 2024-11-12 17:57:28 -06:00
Rose Thompson
383fce5522 Fixed the issue with cbo.clean. 2024-11-12 14:38:44 -06:00
Rose Thompson
b7b7c79726 CBO.FLUSH was not clearing the valid bit if the cacheline was clean. 2024-11-12 14:16:55 -06:00
Rose Thompson
8a4868ac57 Resolved a bug in the cache but there are still mismatches with the cache simulator. 2024-11-12 11:35:29 -06:00
Rose Thompson
3137fd7db2 Resolved some of the issues with the cache simulator mismatching with Wally. The LRU was incorrectly updating it's state while the cache was stalled causin g the LRU state to be update when it should not be. 2024-11-11 14:23:58 -06:00
naichewa
515e05ed75
Merge branch 'openhwgroup:main' into main 2024-11-08 11:07:29 -08:00
naichewa
396a17623b Fixed TransmitStart resetting SCK and delay counter while already counting 2024-11-08 11:05:38 -08:00
Mike Kuskov
e57473ece1 Fix minor typos in src/fpu/postproc 2024-11-08 02:23:44 +03:00
naichewa
e59ca12cdc Merge branch 'main' of https://github.com/naichewa/cvw 2024-11-07 12:14:28 -08:00
naichewa
987015a2a7 Fix SPI Delay1 behavior 2024-11-07 12:14:23 -08:00
naichewa
24509adea3
Merge branch 'openhwgroup:main' into main 2024-11-07 10:49:36 -08:00
naichewa
7964358651 Fix erroneous implicit sckcs and cssck phase delays 2024-11-07 10:47:51 -08:00
naichewa
7637f3e33b Fix erroneous implicit sckcs and cssck phase delays 2024-11-07 10:19:55 -08:00
naichewa
927398a017 Fix SPI state skipping sck-cs delay when at end of transmission 2024-11-07 10:17:22 -08:00
Corey Hickson
1570a6338e Fixed fmvp.d.x bug 2024-11-06 03:32:53 -08:00
Jacob Pease
507c1dad1c Removed impossible condition in receive register logic. 2024-11-04 16:15:42 -06:00
Jacob Pease
120b21d7d5 More SPI optimizations. 2024-11-04 15:38:12 -06:00
Jacob Pease
745e53adf7 Merge branch 'main' of github.com:openhwgroup/cvw 2024-11-04 11:56:15 -06:00
Corey Hickson
0c6e9dc770 Fixed rmm rounding mode bug 2024-11-03 14:21:55 -08:00
Jacob Pease
a9e6962cd4 Removed unused signals and renamed other signals. Removed a bunch of delay counters and simply reuse one counter for all delay types. Tested on FPGA and it also passes regression. 2024-11-03 00:35:40 -05:00
Jacob Pease
674d008f23 Added headers to files. 2024-11-02 14:31:05 -05:00
Jacob Pease
c197d4a3c6 Cleaned up some code. Still more work to do there. 2024-11-01 17:35:55 -05:00
Jacob Pease
e881bd3120 Changed the condition for TransmitStart fsm to avoid edge condition. 2024-11-01 17:04:07 -05:00
Jacob Pease
eddae8e1a6 Fixed ShiftEdge and SampleEdge to not always include PhaseOneOffset. Before, it worked in simulation, but not on the FPGA. 2024-11-01 13:02:17 -05:00
Jacob Pease
56a6ad3376 Fixed lint issues. 2024-10-31 15:56:16 -05:00
Jacob Pease
3ee5fffe02 Fixing latches. 2024-10-31 13:54:56 -05:00
Jacob Pease
72a854eb07 Refactored SPI passes regression save for hardware interlock tests. 2024-10-31 13:01:25 -05:00
Jacob Pease
419030bc33 Fixed FSM to continue transmitting after delay. 2024-10-31 10:41:38 -05:00
Jacob Pease
35c9fe7648 Added changed SPI controller module. New signal TransmitStartD that starts the FSM based on SCLKenable. TransmitStart is responsible for resetting SCLKenable and loading the Transmit Shift Register. 2024-10-30 18:45:54 -05:00
Jacob Pease
4e7e311b26 Fixed issues relating to SCLKenable and TransmitStart. Works at multiple dividers now, instead of just SckDiv = 0. 2024-10-30 18:39:04 -05:00
Jacob Pease
4f0723f236 Fixed enabling of TransmitFIFOReadIncrement and ReceiveFIFOWriteIncrement 2024-10-30 16:19:46 -05:00
Jacob Pease
ca1c09041a Merge branch 'main' of github.com:openhwgroup/cvw 2024-10-30 10:37:02 -05:00
Corey Hickson
b1f340ba5c formatting 2024-10-30 03:39:55 -07:00
Corey Hickson
b9317e7cd3 Fixed fround bug 2024-10-30 03:28:58 -07:00
Jacob Pease
b667581ffa Refactored SPI peripheral based on SPI controller module. Works in tests/custom/spitest. 2024-10-29 17:50:36 -05:00
Jacob Pease
784630b945 Added wally header to spi_controller. 2024-10-29 10:53:33 -05:00
Jacob Pease
37d2f3220e Added a new spi controller design. Designed as a proof of concept to see if timing issues can be fixed. I intend to work it into existing SPI peripheral. 2024-10-29 10:30:08 -05:00
David Harris
1c1acc467e Tweaked SPI to avoid breaking VCS, but the SCLK divider still doesn't produce the right frequency and SCLKenableEarly looks like it wouldn't work for SckDiv = 0 2024-10-26 02:01:09 -07:00
David Harris
da2310fb3e Merge conflict in coverage.svh 2024-10-22 04:48:57 -07:00