mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-23 13:04:28 +00:00
Merge branch 'openhwgroup:main' into main
This commit is contained in:
naichewa
GitHub
commit
515e05ed75
@ -10,13 +10,6 @@
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`include "RV32M_coverage.svh"
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`include "RV32F_coverage.svh"
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`include "RV32D_coverage.svh"
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`include "RV32Zba_coverage.svh"
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`include "RV32Zbb_coverage.svh"
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`include "RV32Zbc_coverage.svh"
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`include "RV32Zbs_coverage.svh"
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`include "RV32Zbkb_coverage.svh"
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`include "RV32Zbkc_coverage.svh"
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`include "RV32Zbkx_coverage.svh"
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`include "RV32ZfaF_coverage.svh"
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`include "RV32ZfaD_coverage.svh"
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`include "RV32ZfaZfh_coverage.svh"
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@ -29,11 +22,6 @@
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`include "RV32ZcbZbb_coverage.svh"
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`include "RV32Zcf_coverage.svh"
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`include "RV32Zcd_coverage.svh"
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`include "RV32Zaamo_coverage.svh"
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`include "RV32Zalrsc_coverage.svh"
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`include "RV32Zknd_coverage.svh"
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`include "RV32Zkne_coverage.svh"
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`include "RV32Zknh_coverage.svh"
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// Privileged extensions
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`include "ZicsrM_coverage.svh"
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@ -71,6 +71,7 @@
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--override no_pseudo_inst=T # For code coverage, don't produce pseudoinstructions
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--override show_c_prefix=T # Show "c." with compressed instructions
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# mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag
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#--override cpu/ecode_mask=0x8000000F # for RV32
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@ -10,16 +10,9 @@
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`include "RV64M_coverage.svh"
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`include "RV64F_coverage.svh"
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`include "RV64D_coverage.svh"
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`include "RV64Zba_coverage.svh"
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`include "RV64Zbb_coverage.svh"
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`include "RV64Zbc_coverage.svh"
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`include "RV64Zbs_coverage.svh"
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`include "RV64Zbkb_coverage.svh"
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`include "RV64Zbkc_coverage.svh"
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`include "RV64Zbkx_coverage.svh"
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`include "RV64ZfaF_coverage.svh"
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`include "RV32ZfaD_coverage.svh"
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`include "RV32ZfaZfh_coverage.svh"
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`include "RV64ZfaD_coverage.svh"
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`include "RV64ZfaZfh_coverage.svh"
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`include "RV64ZfhD_coverage.svh"
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`include "RV64Zfh_coverage.svh"
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`include "RV64Zicond_coverage.svh"
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@ -29,18 +22,6 @@
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`include "RV64ZcbZbb_coverage.svh"
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`include "RV64ZcbZba_coverage.svh"
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`include "RV64Zcd_coverage.svh"
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`include "RV64Zaamo_coverage.svh"
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`include "RV64Zalrsc_coverage.svh"
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`include "RV64Zknd_coverage.svh"
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`include "RV64Zkne_coverage.svh"
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`include "RV64Zknh_coverage.svh"
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// Privileged extensions
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`include "RV64VM_coverage.svh"
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@ -70,6 +70,9 @@
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# For code coverage, don't produce pseudoinstructions
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--override no_pseudo_inst=T
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# Show "c." with compressed instructions
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--override show_c_prefix=T
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# nonratified mnosie register not implemented
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--override cpu/mnoise_undefined=T
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@ -46,14 +46,14 @@ module postprocess import cvw::*; #(parameter cvw_t P) (
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input logic [P.NE+1:0] FmaSe, // the sum's exponent
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input logic [P.FMALEN-1:0] FmaSm, // the positive sum
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input logic FmaASticky, // sticky bit that is calculated during alignment
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input logic [$clog2(P.FMALEN+1)-1:0] FmaSCnt, // the normalization shift count
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input logic [$clog2(P.FMALEN+1)-1:0] FmaSCnt, // the normalization shift count
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//divide signals
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input logic DivSticky, // divider sticky bit
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input logic [P.NE+1:0] DivUe, // divsqrt exponent
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input logic [P.DIVb:0] DivUm, // divsqrt significand
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// conversion signals
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input logic CvtCs, // the result's sign
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input logic [P.NE:0] CvtCe, // the calculated expoent
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input logic [P.NE:0] CvtCe, // the calculated exponent
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input logic CvtResSubnormUf, // the convert result is subnormal or underflows
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input logic [P.LOGCVTLEN-1:0] CvtShiftAmt, // how much to shift by
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input logic ToInt, // is fp->int (since it's writting to the integer register)
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@ -28,7 +28,7 @@ all: $(OBJDUMPS) $(MEMFILES)
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# Assemble into object files
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%.$(OBJEXT): %.$(AEXT)
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riscv64-unknown-elf-as -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 $<
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riscv64-unknown-elf-as -g -o $@ -march=rv64gqc_zcb_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh_svinval -mabi=lp64 $<
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# Preprocess assembly files
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%.$(AEXT): %.$(SRCEXT) WALLY-init-lib.h
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@ -38,6 +38,9 @@ main:
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csrrw t1, menvcfg, t0
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csrrw t2, senvcfg, t0
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# Test writing to TIME CSR
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csrw time, zero
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# testing FIOM with different privilege modes
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# setting environment config (to both 1 and 0) in each privilege mode
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csrsi menvcfg, 1
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@ -1,18 +0,0 @@
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// fround.s
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#include "WALLY-init-lib.h"
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# run-elf.bash find this in project description
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main:
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bseti t0, zero, 14 # turn on FPU
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csrs mstatus, t0
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# test fround behavior on NaN
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li t0, 0x7FC00001
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fmv.w.x ft0, t0
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fround.s ft1, ft0
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j done
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.align 10
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data_start:
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@ -81,6 +81,7 @@ main:
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.word 0xFF00302F // illegal Atomic instruction
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.word 0xFF00402F // illegal Atomic instruction
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.word 0x00000873 // illegal CSR instruction
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.word 0x31bf1f93 // illegal aes64ksli1 instruction
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# Illegal CMO instructions because envcfg is 0 and system is in user Mode
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li a0, 0
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@ -43,35 +43,23 @@ main:
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.hword 0x9C41 // line 134 Illegal compressed instruction
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# Zcb coverage tests
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# could restore assembly language versions when GCC supports Zcb
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mv s0, sp
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#c.lbu s1, 0(s0) // exercise c.lbu
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.hword 0x8004 // c.lbu s1, 0(s0)
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#c.lh s1, 0(s0) // exercise c.lh
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.hword 0x8444 // c.lh s1, 0(s0)
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#c.lhu s1, 0(s0) // exercise c.lhu
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.hword 0x8404 // c.lhu s1, 0(s0)
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#c.sb s1, 0(s0) // exercise c.sb
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.hword 0x8804 // c.sb s1, 0(s0)
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#c.sh s1, 0(s0) // exercise c.sh
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.hword 0x8C04 // c.sh s1, 0(s0)
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c.lbu s1, 0(s0) // exercise c.lbu
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c.lh s1, 0(s0) // exercise c.lh
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c.lhu s1, 0(s0) // exercise c.lhu
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c.sb s1, 0(s0) // exercise c.sb
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c.sh s1, 0(s0) // exercise c.sh
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.hword 0x8C44 // Illegal compressed instruction with op = 00, Instr[15:10] = 100011, Instr[6] = 1 and 0's everywhere else. Line 119 illegal instruction
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.hword 0x9C00 // Illegal compressed instruction with op = 00, Instr[15:10] = 100111, and 0's everywhere else. Line 119 illegal instruction
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li s0, 0xFF
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# c.zext.b s0 // exercise c.zext.b
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.hword 0x9C61 // c.zext.b s0
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# c.sext.b s0 // exercise c.sext.b
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.hword 0x9C65 // c.sext.b s0
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# c.zext.h s0 // exercise c.zext.h
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.hword 0x9C69 // c.zext.h s0
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# c.sext.h s0 // exercise c.sext.h
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.hword 0x9C6D // c.sext.h s0
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# c.zext.w s0 // exercise c.zext.w
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.hword 0x9C71 // c.zext.w s0
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# c.not s0 // exercise c.not
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.hword 0x9C75 // c.not s0
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c.zext.b s0 // exercise c.zext.b
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c.sext.b s0 // exercise c.sext.b
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c.zext.h s0 // exercise c.zext.h
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c.sext.h s0 // exercise c.sext.h
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c.zext.w s0 // exercise c.zext.w
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c.not s0 // exercise c.not
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.hword 0x9C7D // Reserved instruction from line 187 with op = 01, Instr[15:10] = 100111, Instr[6:5] = 11, and 0's everywhere else
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@ -304,7 +304,7 @@ sretdone:
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li a0, 3
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ecall
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# exercise sfence.inval.ir instruction
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.word 0x18100073
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sfence.inval.ir
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# exercise sret with rs1 not 0
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.word 0x102F8073
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