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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Tweaked SPI to avoid breaking VCS, but the SCLK divider still doesn't produce the right frequency and SCLKenableEarly looks like it wouldn't work for SckDiv = 0
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@ -234,9 +234,9 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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// SPI enable generation, where SCLK = PCLK/(2*(SckDiv + 1))
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// Asserts SCLKenable at the rising and falling edge of SCLK by counting from 0 to SckDiv
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// Active at 2x SCLK frequency to account for implicit half cycle delays and actions on both clock edges depending on phase
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// When SckDiv is 0, count doesn't work and SCLKenable is simply PCLK
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// When SckDiv is 0, count doesn't work and SCLKenable is simply PCLK *** dh 10/26/24: this logic is seriously broken. SCLK is not scaled to PCLK/(2*(SckDiv + 1)). SCLKenableEarly doesn't work right for SckDiv=0
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assign ZeroDiv = ~|(SckDiv[10:0]);
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assign SCLKenable = ZeroDiv ? PCLK : (DivCounter == SckDiv);
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assign SCLKenable = ZeroDiv ? 1 : (DivCounter == SckDiv);
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assign SCLKenableEarly = ((DivCounter + 12'b1) == SckDiv);
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always_ff @(posedge PCLK)
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if (~PRESETn) DivCounter <= '0;
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@ -32,59 +32,59 @@
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00000003
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00000074
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00000074 # spi_burst_send
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00000063
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00000063 # spi_burst_send
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00000052
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00000052 # spi_burst_send
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00000041
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00000041 # spi_burst_send
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000000A1
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000000A1 # spi_burst_send
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00000003
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000000B2
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000000B2 # spi_burst_send
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00000001
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000000C3
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000000C3 # spi_burst_send
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000000D4
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000000D4 # spi_burst_send
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00000003
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000000A4
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000000A4 # tx_data write test
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00000001
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000000B4
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000000B4 # tx_data write test
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000000A5
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000000A5 # spi_burst_send
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000000B5
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000000B5 # spi_burst_send
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000000C5
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000000C5 # spi_burst_send
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000000D5
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000000D5 # spi_burst_send
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000000A7
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000000A7 # spi_burst_send
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000000B7
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000000B7 # spi_burst_send
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000000C7
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000000C7 # spi_burst_send
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00000002
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000000D7
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000000D7 # spi_burst_send
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00000000
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00000011 #basic read write
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000000FF
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000000FF # first test sck_div
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000000AE
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000000AE # min sck_div first spi_burst_send
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000000AD
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