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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Refactored SPI passes regression save for hardware interlock tests.
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419030bc33
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72a854eb07
@ -86,6 +86,7 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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logic EndOfFrameDelay;
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logic Transmitting;
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logic InactiveState;
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logic [3:0] FrameLength;
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logic ResetSCLKenable;
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logic TransmitStart;
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@ -213,12 +214,13 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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// SPI Controller module -------------------------------------------
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// This module controls state and timing signals that drive the rest of this module
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assign ResetSCLKenable = Memwrite & (Entry == SPI_SCKDIV);
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assign FrameLength = Format[4:1];
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spi_controller controller(PCLK, PRESETn,
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// Transmit Signals
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TransmitStart, TransmitStartD, ResetSCLKenable,
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// Register Inputs
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SckDiv, SckMode, ChipSelectMode, Delay0, Delay1,
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SckDiv, SckMode, ChipSelectMode, Delay0, Delay1, FrameLength,
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// txFIFO stuff
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TransmitFIFOReadEmpty,
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// Timing
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@ -243,6 +245,19 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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TransmitFIFOReadIncrement <= TransmitStartD | (EndOfFrameDelay & ~TransmitFIFOReadEmpty) ;
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end
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// Check whether TransmitReg has been loaded.
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// We use this signal to prevent returning to the Ready state for TransmitStart
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logic TransmitRegLoaded;
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always_ff @(posedge PCLK) begin
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if (~PRESETn) begin
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TransmitRegLoaded <= 1'b0;
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end else if (TransmitLoad) begin
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TransmitRegLoaded <= 1'b1;
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end else if (ShiftEdge | EndOfFrameDelay) begin
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TransmitRegLoaded <= 1'b0;
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end
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end
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// Setup TransmitStart state machine
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always_ff @(posedge PCLK) begin
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if (~PRESETn) begin
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@ -251,14 +266,14 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
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CurrState <= NextState;
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end
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end
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// State machine for starting transmissions
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always_comb begin
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case (CurrState)
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READY: if (~TransmitFIFOReadEmpty & ~Transmitting) NextState = START;
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else NextState = READY;
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START: NextState = WAIT;
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WAIT: if (TransmitFIFOReadEmpty & ~Transmitting) NextState = READY;
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WAIT: if (TransmitFIFOReadEmpty & ~Transmitting & ~TransmitRegLoaded) NextState = READY;
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else NextState = WAIT;
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endcase
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end
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@ -43,6 +43,7 @@ module spi_controller (
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input logic [1:0] CSMode,
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input logic [15:0] Delay0,
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input logic [15:0] Delay1,
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input logic [3:0] FrameLength,
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// Is the Transmit FIFO Empty?
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input logic txFIFOReadEmpty,
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@ -146,7 +147,7 @@ module spi_controller (
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assign SCLKenable = DivCounter == SckDiv;
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// assign SCLKenableEarly = (DivCounter + 1'b1) == SckDiv;
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assign LastBit = BitNum == 3'd7;
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assign LastBit = (BitNum == FrameLength - 4'b1);
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//assign EndOfFrame = SCLKenable & LastBit & Transmitting;
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assign ContinueTransmit = ~txFIFOReadEmpty & EndOfFrameDelay;
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@ -161,6 +162,10 @@ module spi_controller (
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PreShiftEdge <= 0;
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PreSampleEdge <= 0;
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EndOfFrame <= 0;
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CSSCKCounter <= 0;
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SCKCSCounter <= 0;
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INTERCSCounter <= 0;
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INTERXFRCounter <= 0;
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end else begin
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// TODO: Consolidate into one delay counter since none of the
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// delays happen at the same time?
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@ -172,25 +177,25 @@ module spi_controller (
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if ((CurrState == CSSCK) & SCK & SCLKenable) begin
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CSSCKCounter <= CSSCKCounter + 8'd1;
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end else if (SCLKenable) begin
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end else if (SCLKenable & EndOfCSSCK) begin
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CSSCKCounter <= 8'd0;
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end
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if ((CurrState == SCKCS) & SCK & SCLKenable) begin
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SCKCSCounter <= SCKCSCounter + 8'd1;
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end else if (SCLKenable) begin
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end else if (SCLKenable & EndOfSCKCS) begin
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SCKCSCounter <= 8'd0;
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end
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if ((CurrState == INTERCS) & SCK & SCLKenable) begin
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INTERCSCounter <= INTERCSCounter + 8'd1;
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end else if (SCLKenable) begin
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end else if (SCLKenable & EndOfINTERCS) begin
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INTERCSCounter <= 8'd0;
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end
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if ((CurrState == INTERXFR) & SCK & SCLKenable) begin
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INTERXFRCounter <= INTERXFRCounter + 8'd1;
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end else if (SCLKenable) begin
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end else if (SCLKenable & EndOfINTERXFR) begin
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INTERXFRCounter <= 8'd0;
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end
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@ -239,7 +244,7 @@ module spi_controller (
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EndOfFrameDelay <= 0;
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end else begin
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ShiftEdge <= ((SckMode[1] ^ SckMode[0] ^ SPICLK) & SCLKenable & ~LastBit & Transmitting) & PhaseOneOffset;
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PhaseOneOffset <= PhaseOneOffset == 0 ? Transmitting & SCLKenable : PhaseOneOffset;
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PhaseOneOffset <= PhaseOneOffset == 0 ? Transmitting & SCLKenable : ~EndOfFrameDelay;
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SampleEdge <= (SckMode[1] ^ SckMode[0] ^ ~SPICLK) & SCLKenable & Transmitting & ~DelayIsNext;
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EndOfFrameDelay <= (SckMode[1] ^ SckMode[0] ^ SPICLK) & SCLKenable & LastBit & Transmitting;
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end
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@ -251,6 +256,23 @@ module spi_controller (
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assign HoldMode = CSMode == HOLDMODE;
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// assign TransmitLoad = TransmitStart | (EndOfFrameDelay & ~txFIFOReadEmpty);
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logic ContinueTransmitD;
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logic NextEndDelay;
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logic CurrentEndDelay;
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assign NextEndDelay = NextState == SCKCS | NextState == INTERCS | NextState == INTERXFR;
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assign CurrentEndDelay = CurrState == SCKCS | CurrState == INTERCS | CurrState == INTERXFR;
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always_ff @(posedge PCLK) begin
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if (~PRESETn) begin
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ContinueTransmitD <= 1'b0;
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end else if (NextEndDelay & ~CurrentEndDelay) begin
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ContinueTransmitD <= ContinueTransmit;
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end else if (EndOfSCKCS & SCLKenable) begin
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ContinueTransmitD <= 1'b0;
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end
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end
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always_ff @(posedge PCLK) begin
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if (~PRESETn) begin
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CurrState <= INACTIVE;
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@ -261,17 +283,19 @@ module spi_controller (
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always_comb begin
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case (CurrState)
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INACTIVE: if (TransmitStartD)
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INACTIVE: if (TransmitStartD) begin
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if (~HasCSSCK) NextState = TRANSMIT;
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else NextState = CSSCK;
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else NextState = INACTIVE;
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end else begin
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NextState = INACTIVE;
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end
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CSSCK: if (EndOfCSSCK) NextState = TRANSMIT;
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else NextState = CSSCK;
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TRANSMIT: begin // TRANSMIT case --------------------------------
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case(CSMode)
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AUTOMODE: begin
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if (EndTransmission) NextState = INACTIVE;
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else if (ContinueTransmit) NextState = SCKCS;
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else if (EndOfFrameDelay) NextState = SCKCS;
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end
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HOLDMODE: begin
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if (EndTransmission) NextState = HOLD;
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@ -279,19 +303,22 @@ module spi_controller (
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else NextState = TRANSMIT;
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end
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OFFMODE: begin
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if (EndTransmission) NextState = INACTIVE;
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else if (ContinueTransmit & HasINTERXFR) NextState = INTERXFR;
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else NextState = TRANSMIT;
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end
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endcase
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end
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SCKCS: begin // SCKCS case --------------------------------------
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if (EndOfSCKCS)
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if (txFIFOReadEmpty) begin
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if (EndOfSCKCS) begin
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if (~ContinueTransmitD) begin
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if (CSMode == AUTOMODE) NextState = INACTIVE;
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else if (CSMode == HOLDMODE) NextState = HOLD;
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end else if (~txFIFOReadEmpty) begin
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end else begin
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if (HasINTERCS) NextState = INTERCS;
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else NextState = TRANSMIT;
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end
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end
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end
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HOLD: begin // HOLD mode case -----------------------------------
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if (CSMode == AUTOMODE) begin
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