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Better name for CacheSetTag2.

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This commit is contained in:
Rose Thompson 2024-11-13 12:24:35 -06:00
parent db3a7d5bbd
commit e22f30ec14
2 changed files with 9 additions and 9 deletions
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12
src/cache/cache.sv vendored
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@ -75,9 +75,9 @@ module cache import cvw::*; #(parameter cvw_t P,
logic SelAdrData;
logic SelAdrTag;
logic [1:0] AdrSelMuxSelData;
logic [1:0] AdrSelMuxSelTag, AdrSelMuxSelTag2;
logic [1:0] AdrSelMuxSelTag, AdrSelMuxSelLRU;
logic [SETLEN-1:0] CacheSetData;
logic [SETLEN-1:0] CacheSetTag, CacheSetTag2;
logic [SETLEN-1:0] CacheSetTag, CacheSetLRU;
logic [LINELEN-1:0] LineWriteData;
logic ClearDirty, SetDirty, SetValid, ClearValid;
logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0];
@ -117,9 +117,9 @@ module cache import cvw::*; #(parameter cvw_t P,
mux3 #(SETLEN) AdrSelMuxTag(NextSet[SETTOP-1:OFFSETLEN], PAdr[SETTOP-1:OFFSETLEN], FlushAdr,
AdrSelMuxSelTag, CacheSetTag);
assign AdrSelMuxSelTag2 = {FlushCache, ((SelAdrTag | SelHPTW | Stall) & ~((READ_ONLY_CACHE == 1) & FlushStage))};
mux3 #(SETLEN) AdrSelMuxTag2(NextSet[SETTOP-1:OFFSETLEN], PAdr[SETTOP-1:OFFSETLEN], FlushAdr,
AdrSelMuxSelTag2, CacheSetTag2);
assign AdrSelMuxSelLRU = {FlushCache, ((SelAdrTag | SelHPTW | Stall) & ~((READ_ONLY_CACHE == 1) & FlushStage))};
mux3 #(SETLEN) AdrSelMuxLRU(NextSet[SETTOP-1:OFFSETLEN], PAdr[SETTOP-1:OFFSETLEN], FlushAdr,
AdrSelMuxSelLRU, CacheSetLRU);
// Array of cache ways, along with victim, hit, dirty, and read merging logic
cacheway #(P, PA_BITS, XLEN, NUMSETS, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
@ -130,7 +130,7 @@ module cache import cvw::*; #(parameter cvw_t P,
// Select victim way for associative caches
if(NUMWAYS > 1) begin:vict
cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMSETS) cacheLRU(
.clk, .reset, .FlushStage, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSetTag(CacheSetTag2), .LRUWriteEn,
.clk, .reset, .FlushStage, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSetLRU, .LRUWriteEn,
.SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache);
end else
assign VictimWay = 1'b1; // one hot.

6
src/cache/cacheLRU.sv vendored
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@ -36,7 +36,7 @@ module cacheLRU
input logic CacheEn, // Enable the cache memory arrays. Disable hold read data constant
input logic [NUMWAYS-1:0] HitWay, // Which way is valid and matches PAdr's tag
input logic [NUMWAYS-1:0] ValidWay, // Which ways for a particular set are valid, ignores tag
input logic [SETLEN-1:0] CacheSetTag, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
input logic [SETLEN-1:0] CacheSetLRU, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
input logic [SETLEN-1:0] PAdr, // Physical address
input logic LRUWriteEn, // Update the LRU state
input logic SetValid, // Set the dirty bit in the selected way and set
@ -142,8 +142,8 @@ module cacheLRU
else if (CacheEn & LRUWriteEn) LRUMemory[PAdr] <= NextLRU;
// LRU read path with write forwarding
assign ReadLRU = LRUMemory[CacheSetTag];
assign ForwardLRU = LRUWriteEn & (PAdr == CacheSetTag);
assign ReadLRU = LRUMemory[CacheSetLRU];
assign ForwardLRU = LRUWriteEn & (PAdr == CacheSetLRU);
mux2 #(NUMWAYS-1) ReadLRUmux(ReadLRU, NextLRU, ForwardLRU, BypassedLRU);
flop #(NUMWAYS-1) CurrLRUReg(clk, BypassedLRU, CurrLRU);
endmodule