Removed impossible condition in receive register logic.

src/uncore/spi_controller.sv

@@ -45,7 +45,7 @@ module spi_controller (
   input logic [3:0]  FrameLength,
 
   // Is the Transmit FIFO Empty?
-  input logic        txFIFOReadEmpty,
+  input logic        TransmitFIFOEmpty,
 
   // Control signals
   output logic       SCLKenable,
@@ -140,8 +140,8 @@ module spi_controller (
   // Active at 2x SCLK frequency to account for implicit half cycle delays and actions on both clock edges depending on phase
   assign SCLKenable = DivCounter == SckDiv;
 
-  assign ContinueTransmit = ~txFIFOReadEmpty & EndOfFrame;
-  assign EndTransmission = txFIFOReadEmpty & EndOfFrame;
+  assign ContinueTransmit = ~TransmitFIFOEmpty & EndOfFrame;
+  assign EndTransmission = TransmitFIFOEmpty & EndOfFrame;
   
   always_ff @(posedge PCLK) begin
     if (~PRESETn) begin

src/uncore/spi_fifo.sv

@@ -19,6 +19,10 @@ module spi_fifo #(parameter M=3, N=8)(                 // 2^M entries of N bits
     logic [M:0] rptrnext, wptrnext;
     logic [M-1:0] raddr;
     logic [M-1:0] waddr;
+
+  logic [M-1:0] numVals;
+  
+  assign numVals = waddr - raddr;
  
     assign rdata = mem[raddr];
     always_ff @(posedge PCLK)