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https://github.com/openhwgroup/cvw
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Added a new spi controller design. Designed as a proof of concept to see if timing issues can be fixed. I intend to work it into existing SPI peripheral.
This commit is contained in:
Jacob Pease
parent
13df786b87
commit
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317
src/uncore/spi_controller.sv
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317
src/uncore/spi_controller.sv
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module spi_controller (
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input logic PCLK,
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input logic PRESETn,
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input logic TransmitStart,
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input logic [11:0] SckDiv,
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input logic [1:0] SckMode,
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input logic [1:0] CSMode,
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input logic [15:0] Delay0,
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input logic [15:0] Delay1,
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input logic [7:0] txFIFORead,
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input logic txFIFOReadEmpty,
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output logic SPICLK,
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output logic SPIOUT,
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output logic CS
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);
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// CSMode Stuff
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localparam HOLDMODE = 2'b10;
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localparam AUTOMODE = 2'b00;
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localparam OFFMODE = 2'b11;
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typedef enum logic [2:0] {INACTIVE, CSSCK, TRANSMIT, SCKCS, HOLD, INTERCS, INTERXFR} statetype;
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statetype CurrState, NextState;
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// SCLKenable stuff
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logic [11:0] DivCounter;
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logic SCLKenable;
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logic SCLKenableEarly;
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logic SCLKenableLate;
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logic EdgeTiming;
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logic ZeroDiv;
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logic Clock0;
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logic Clock1;
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logic SCK; // SUPER IMPORTANT, THIS CAN'T BE THE SAME AS SPICLK!
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// Shift and Sample Edges
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logic PreShiftEdge;
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logic PreSampleEdge;
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logic ShiftEdge;
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logic SampleEdge;
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// Frame stuff
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logic [2:0] BitNum;
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logic LastBit;
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logic EndOfFrame;
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logic EndOfFrameDelay;
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logic PhaseOneOffset;
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// Transmit Stuff
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logic ContinueTransmit;
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// SPIOUT Stuff
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logic TransmitLoad;
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logic [7:0] TransmitReg;
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logic Transmitting;
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logic EndTransmission;
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logic HoldMode;
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// Delay Stuff
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logic [7:0] cssck;
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logic [7:0] sckcs;
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logic [7:0] intercs;
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logic [7:0] interxfr;
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logic HasCSSCK;
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logic HasSCKCS;
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logic HasINTERCS;
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logic HasINTERXFR;
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logic EndOfCSSCK;
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logic EndOfSCKCS;
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logic EndOfINTERCS;
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logic EndOfINTERXFR;
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logic [7:0] CSSCKCounter;
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logic [7:0] SCKCSCounter;
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logic [7:0] INTERCSCounter;
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logic [7:0] INTERXFRCounter;
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logic DelayIsNext;
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// Convenient Delay Reg Names
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assign cssck = Delay0[7:0];
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assign sckcs = Delay0[15:8];
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assign intercs = Delay1[7:0];
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assign interxfr = Delay1[15:8];
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// Do we have delay for anything?
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assign HasCSSCK = cssck > 8'b0;
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assign HasSCKCS = sckcs > 8'b0;
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assign HasINTERCS = intercs > 8'b0;
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assign HasINTERXFR = interxfr > 8'b0;
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// Have we hit full delay for any of the delays?
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assign EndOfCSSCK = CSSCKCounter == cssck;
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assign EndOfSCKCS = SCKCSCounter == sckcs;
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assign EndOfINTERCS = INTERCSCounter == intercs;
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assign EndOfINTERXFR = INTERXFRCounter == interxfr;
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// Clock Signal Stuff -----------------------------------------------
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// I'm going to handle all clock stuff here, including ShiftEdge and
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// SampleEdge. This makes sure that SPICLK is an output of a register
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// and it properly synchronizes signals.
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assign SCLKenableLate = DivCounter > SckDiv;
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assign SCLKenable = DivCounter == SckDiv;
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assign SCLKenableEarly = (DivCounter + 1'b1) == SckDiv;
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assign LastBit = BitNum == 3'd7;
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assign EdgeTiming = SckDiv > 12'b0 ? SCLKenableEarly : SCLKenable;
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//assign SPICLK = Clock0;
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assign ContinueTransmit = ~txFIFOReadEmpty & EndOfFrame;
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assign EndTransmission = txFIFOReadEmpty & EndOfFrameDelay;
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always_ff @(posedge PCLK) begin
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if (~PRESETn) begin
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DivCounter <= 12'b0;
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SPICLK <= SckMode[1];
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SCK <= 0;
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BitNum <= 3'h0;
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PreShiftEdge <= 0;
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PreSampleEdge <= 0;
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EndOfFrame <= 0;
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end else begin
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// TODO: Consolidate into one delay counter since none of the
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// delays happen at the same time?
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if (TransmitStart) begin
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SCK <= 0;
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end else if (SCLKenable) begin
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SCK <= ~SCK;
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end
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if ((CurrState == CSSCK) & SCK) begin
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CSSCKCounter <= CSSCKCounter + 8'd1;
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end else begin
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CSSCKCounter <= 8'd0;
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end
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if ((CurrState == SCKCS) & SCK) begin
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SCKCSCounter <= SCKCSCounter + 8'd1;
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end else begin
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SCKCSCounter <= 8'd0;
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end
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if ((CurrState == INTERCS) & SCK) begin
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INTERCSCounter <= INTERCSCounter + 8'd1;
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end else begin
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INTERCSCounter <= 8'd0;
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end
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if ((CurrState == INTERXFR) & SCK) begin
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INTERXFRCounter <= INTERXFRCounter + 8'd1;
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end else begin
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INTERXFRCounter <= 8'd0;
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end
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// SPICLK Logic
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if (TransmitStart) begin
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SPICLK <= SckMode[1];
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end else if (SCLKenable & Transmitting) begin
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SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1];
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end
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// Reset divider
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if (SCLKenable | TransmitStart) begin
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DivCounter <= 12'b0;
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end else begin
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DivCounter = DivCounter + 12'd1;
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end
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// EndOfFrame controller
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// if (SckDiv > 0 ? SCLKenableEarly & LastBit & SPICLK : LastBit & ~SPICLK) begin
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// EndOfFrame <= 1'b1;
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// end else begin
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// EndOfFrame <= 1'b0;
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// end
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if (~TransmitStart) begin
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EndOfFrame <= (SckMode[1] ^ SckMode[0] ^ SPICLK) & SCLKenable & LastBit & Transmitting;
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end
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// Increment BitNum
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if (ShiftEdge & Transmitting) begin
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BitNum <= BitNum + 3'd1;
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end else if (EndOfFrameDelay) begin
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BitNum <= 3'b0;
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end
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end
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end
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// Delay ShiftEdge and SampleEdge by a half PCLK period
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// Aligned EXACTLY ON THE MIDDLE of the leading and trailing edges.
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// Sweeeeeeeeeet...
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always_ff @(posedge ~PCLK) begin
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if (~PRESETn | TransmitStart) begin
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ShiftEdge <= 0;
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PhaseOneOffset <= 0;
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SampleEdge <= 0;
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EndOfFrameDelay <= 0;
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end else begin
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ShiftEdge <= ((SckMode[1] ^ SckMode[0] ^ SPICLK) & SCLKenable & ~LastBit & Transmitting) & PhaseOneOffset;
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PhaseOneOffset <= PhaseOneOffset == 0 ? Transmitting & SCLKenable : PhaseOneOffset;
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SampleEdge <= (SckMode[1] ^ SckMode[0] ^ ~SPICLK) & SCLKenable & Transmitting;
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EndOfFrameDelay <= (SckMode[1] ^ SckMode[0] ^ SPICLK) & SCLKenable & LastBit & Transmitting;
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end
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end
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// typedef enum logic [2:0] {INACTIVE, CSSCK, TRANSMIT, SCKCS, HOLD, INTERCS, INTERXFR} statetype;
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// statetype CurrState, NextState;
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assign HoldMode = CSMode == 2'b10;
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assign TransmitLoad = TransmitStart | (EndOfFrameDelay & ~txFIFOReadEmpty);
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always_ff @(posedge PCLK) begin
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if (~PRESETn) begin
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CurrState <= INACTIVE;
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end else if (SCLKenable) begin
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CurrState <= NextState;
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end
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end
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always_comb begin
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case (CurrState)
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INACTIVE: begin // INACTIVE case --------------------------------
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if (TransmitStart) begin
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if (~HasCSSCK) begin
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NextState = TRANSMIT;
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end else begin
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NextState = CSSCK;
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end
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end else begin
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NextState = INACTIVE;
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end
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end
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CSSCK: begin // DELAY0 case -------------------------------------
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if (EndOfCSSCK) begin
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NextState = TRANSMIT;
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end
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end
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TRANSMIT: begin // TRANSMIT case --------------------------------
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case(CSMode)
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AUTOMODE: begin
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if (EndTransmission) begin
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NextState = INACTIVE;
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end else if (ContinueTransmit) begin
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NextState = SCKCS;
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end
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end
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HOLDMODE: begin
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if (EndTransmission) begin
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NextState = HOLD;
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end else if (ContinueTransmit) begin
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if (HasINTERXFR) NextState = INTERXFR;
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end
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end
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OFFMODE: begin
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end
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endcase
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end
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SCKCS: begin // SCKCS case --------------------------------------
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if (EndOfSCKCS) begin
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if (EndTransmission) begin
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if (CSMode == AUTOMODE) NextState = INACTIVE;
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else if (CSMode == HOLDMODE) NextState = HOLD;
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end else if (ContinueTransmit) begin
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if (HasINTERCS) NextState = INTERCS;
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else NextState = TRANSMIT;
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end
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end
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end
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HOLD: begin // HOLD mode case -----------------------------------
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if (CSMode == AUTOMODE) begin
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NextState = INACTIVE;
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end else if (TransmitStart) begin // If FIFO is written to, start again.
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NextState = TRANSMIT;
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end
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end
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INTERCS: begin // INTERCS case ----------------------------------
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if (EndOfINTERCS) begin
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if (HasCSSCK) NextState = CSSCK;
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else NextState = TRANSMIT;
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end
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end
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INTERXFR: begin // INTERXFR case --------------------------------
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if (EndOfINTERXFR) begin
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NextState = TRANSMIT;
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end
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end
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default: begin
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NextState = INACTIVE;
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end
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endcase
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end
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assign Transmitting = CurrState == TRANSMIT;
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assign DelayIsNext = (NextState == CSSCK | NextState == SCKCS | NextState == INTERCS | NextState == INTERXFR);
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//
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always_ff @(posedge PCLK) begin
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if (~PRESETn) begin
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TransmitReg <= 8'b0;
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end else if (TransmitLoad) begin
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TransmitReg <= txFIFORead;
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end else if (ShiftEdge) begin
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TransmitReg <= {TransmitReg[6:0], TransmitReg[0]};
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end
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end
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assign SPIOUT = TransmitReg[7];
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assign CS = CurrState == INACTIVE | CurrState == INTERCS;
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endmodule
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