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https://github.com/openhwgroup/cvw
synced 2025-01-22 20:44:28 +00:00
More lint cleanup: remove unused params
This commit is contained in:
Jordan Carlin
parent
a462b9a2e6
commit
f6b0805fd4
@ -30,7 +30,7 @@ for config in ${configs[@]}; do
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if !($verilator --lint-only --quiet --top-module wallywrapper \
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"-I$basepath/config/shared" "-I$basepath/config/$config" "-I$basepath/config/deriv/$config" \
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$basepath/src/cvw.sv $basepath/testbench/wallywrapper.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv \
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-Wall -Wno-UNUSEDSIGNAL -Wno-UNUSEDPARAM -Wno-VARHIDDEN -Wno-GENUNNAMED -Wno-PINCONNECTEMPTY); then
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-Wall -Wno-UNUSEDSIGNAL -Wno-VARHIDDEN -Wno-GENUNNAMED -Wno-PINCONNECTEMPTY); then
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if [ "$1" == "-nightly" ]; then
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echo -e "${RED}$config failed lint${NC}"
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fails=$((fails+1))
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18
src/cache/cache.sv
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18
src/cache/cache.sv
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@ -29,7 +29,7 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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module cache import cvw::*; #(parameter cvw_t P,
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parameter PA_BITS, XLEN, LINELEN, NUMSETS, NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) (
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parameter PA_BITS, LINELEN, NUMSETS, NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, READ_ONLY_CACHE) (
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input logic clk,
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input logic reset,
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input logic Stall, // Stall the cache, preventing new accesses. In-flight access finished but does not return to READY
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@ -66,11 +66,7 @@ module cache import cvw::*; #(parameter cvw_t P,
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localparam SETLEN = $clog2(NUMSETS); // Number of set bits
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localparam SETTOP = SETLEN+OFFSETLEN; // Number of set plus offset bits
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localparam TAGLEN = PA_BITS - SETTOP; // Number of tag bits
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localparam CACHEWORDSPERLINE = LINELEN/WORDLEN;// Number of words in cache line
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localparam LOGCWPL = $clog2(CACHEWORDSPERLINE);// Log2 of ^
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localparam FLUSHADRTHRESHOLD = NUMSETS - 1; // Used to determine when flush is complete
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localparam LOGLLENBYTES = $clog2(WORDLEN/8); // Number of bits to address a word
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logic SelAdrData;
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logic SelAdrTag;
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@ -122,14 +118,14 @@ module cache import cvw::*; #(parameter cvw_t P,
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AdrSelMuxSelLRU, CacheSetLRU);
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// Array of cache ways, along with victim, hit, dirty, and read merging logic
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cacheway #(P, PA_BITS, XLEN, NUMSETS, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
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cacheway #(P, PA_BITS, NUMSETS, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
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.clk, .reset, .CacheEn, .CacheSetData, .CacheSetTag, .PAdr, .LineWriteData, .LineByteMask, .SelVictim,
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.SetValid, .ClearValid, .SetDirty, .ClearDirty, .VictimWay,
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.FlushWay, .FlushCache, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .HitDirtyWay, .TagWay, .FlushStage, .InvalidateCache);
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// Select victim way for associative caches
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if(NUMWAYS > 1) begin:vict
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cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMSETS) cacheLRU(
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cacheLRU #(NUMWAYS, SETLEN, NUMSETS) cacheLRU(
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.clk, .reset, .FlushStage, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSetLRU, .LRUWriteEn,
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.SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache);
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end else
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@ -172,11 +168,7 @@ module cache import cvw::*; #(parameter cvw_t P,
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if(!READ_ONLY_CACHE) begin:WriteSelLogic
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logic [LINELEN/8-1:0] DemuxedByteMask, FetchBufferByteSel;
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// Adjust byte mask from word to cache line
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localparam CACHEMUXINVERALPERLINE = LINELEN/MUXINTERVAL;// Number of words in cache line
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localparam LOGMIPL = $clog2(CACHEMUXINVERALPERLINE);// Log2 of ^
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// Adjust byte mask from word to cache line
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logic [LINELEN/8-1:0] BlankByteMask;
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assign BlankByteMask[WORDLEN/8-1:0] = ByteMask;
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assign BlankByteMask[LINELEN/8-1:WORDLEN/8] = 0;
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@ -231,7 +223,7 @@ module cache import cvw::*; #(parameter cvw_t P,
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// Cache FSM
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/////////////////////////////////////////////////////////////////////////////////////////////
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cachefsm #(P, READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck,
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cachefsm #(READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck,
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.FlushStage, .CacheRW, .Stall,
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.Hit, .LineDirty, .HitLineDirty, .CacheStall, .CacheCommitted,
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.CacheMiss, .CacheAccess, .SelAdrData, .SelAdrTag, .SelVictim,
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2
src/cache/cacheLRU.sv
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2
src/cache/cacheLRU.sv
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@ -29,7 +29,7 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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module cacheLRU
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#(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMSETS = 128) (
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#(parameter NUMWAYS = 4, SETLEN = 9, NUMSETS = 128) (
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input logic clk,
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input logic reset,
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input logic FlushStage,
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3
src/cache/cachefsm.sv
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3
src/cache/cachefsm.sv
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@ -28,8 +28,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module cachefsm import cvw::*; #(parameter cvw_t P,
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parameter READ_ONLY_CACHE = 0) (
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module cachefsm #(parameter READ_ONLY_CACHE = 0) (
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input logic clk,
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input logic reset,
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// hazard and privilege unit
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9
src/cache/cacheway.sv
vendored
9
src/cache/cacheway.sv
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@ -29,7 +29,7 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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module cacheway import cvw::*; #(parameter cvw_t P,
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parameter PA_BITS, XLEN, NUMSETS=512, LINELEN = 256, TAGLEN = 26,
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parameter PA_BITS, NUMSETS=512, LINELEN = 256, TAGLEN = 26,
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OFFSETLEN = 5, INDEXLEN = 9, READ_ONLY_CACHE = 0) (
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input logic clk,
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input logic reset,
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@ -57,12 +57,6 @@ module cacheway import cvw::*; #(parameter cvw_t P,
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output logic DirtyWay , // The selected way is dirty
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output logic [TAGLEN-1:0] TagWay); // This way's tag if valid
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localparam WORDSPERLINE = LINELEN/XLEN;
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localparam BYTESPERLINE = LINELEN/8;
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localparam LOGWPL = $clog2(WORDSPERLINE);
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localparam LOGXLENBYTES = $clog2(XLEN/8);
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localparam BYTESPERWORD = XLEN/8;
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logic [NUMSETS-1:0] ValidBits;
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logic [NUMSETS-1:0] DirtyBits;
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logic [LINELEN-1:0] ReadDataLine;
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@ -131,7 +125,6 @@ module cacheway import cvw::*; #(parameter cvw_t P,
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localparam NUMSRAM = LINELEN/P.CACHE_SRAMLEN;
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localparam SRAMLENINBYTES = P.CACHE_SRAMLEN/8;
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localparam LOGNUMSRAM = $clog2(NUMSRAM);
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for(words = 0; words < NUMSRAM; words++) begin: word
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if (READ_ONLY_CACHE) begin:wordram // no byte-enable needed for i$.
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@ -27,7 +27,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module hazard import cvw::*; #(parameter cvw_t P) (
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module hazard (
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input logic BPWrongE, CSRWriteFenceM, RetM, TrapM,
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input logic StructuralStallD,
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input logic LSUStallM, IFUStallF,
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@ -236,7 +236,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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assign BusRW = ~ITLBMissF & ~CacheableF & ~SelIROM ? IFURWF : '0;
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assign CacheRWF = ~ITLBMissF & CacheableF & ~SelIROM ? IFURWF : '0;
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cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.ICACHE_LINELENINBITS),
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cache #(.P(P), .PA_BITS(P.PA_BITS), .LINELEN(P.ICACHE_LINELENINBITS),
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.NUMSETS(P.ICACHE_WAYSIZEINBYTES*8/P.ICACHE_LINELENINBITS),
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.NUMWAYS(P.ICACHE_NUMWAYS), .LOGBWPL(AHBWLOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .READ_ONLY_CACHE(1))
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icache(.clk, .reset, .FlushStage(FlushD), .Stall(GatedStallD),
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@ -324,7 +324,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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assign CacheRWM = (CacheableM & ~SelDTIM) ? LSURWM : '0;
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assign FlushDCache = FlushDCacheM & ~(SelHPTW);
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cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMSETS(P.DCACHE_WAYSIZEINBYTES*8/LINELEN),
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cache #(.P(P), .PA_BITS(P.PA_BITS), .LINELEN(P.DCACHE_LINELENINBITS), .NUMSETS(P.DCACHE_WAYSIZEINBYTES*8/LINELEN),
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.NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(CACHEWORDLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache(
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.clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(LSUFlushW),
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.CacheRW(CacheRWM),
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@ -67,8 +67,6 @@ module csrs import cvw::*; #(parameter cvw_t P) (
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localparam STIMECMPH = 12'h15D;
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localparam SATP = 12'h180;
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// Constants
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localparam ZERO = {(P.XLEN){1'b0}};
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localparam SEDELEG_MASK = ~(ZERO | {{P.XLEN-3{1'b0}}, 3'b111} << 9);
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logic WriteSTVECM;
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logic WriteSSCRATCHM, WriteSEPCM;
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@ -28,7 +28,7 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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module ram_ahb import cvw::*; #(parameter cvw_t P,
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parameter BASE=0, RANGE = 65535, PRELOAD = 0) (
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parameter RANGE = 65535, PRELOAD = 0) (
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input logic HCLK, HRESETn,
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input logic HSELRam,
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input logic [P.PA_BITS-1:0] HADDR,
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@ -28,7 +28,7 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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module rom_ahb import cvw::*; #(parameter cvw_t P,
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parameter BASE=0, RANGE = 65535, PRELOAD = 0) (
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parameter RANGE = 65535, PRELOAD = 0) (
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input logic HCLK, HRESETn,
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input logic HSELRom,
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input logic [P.PA_BITS-1:0] HADDR,
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@ -109,13 +109,13 @@ module uncore import cvw::*; #(parameter cvw_t P)(
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// on-chip RAM
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if (P.UNCORE_RAM_SUPPORTED) begin : ram
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ram_ahb #(.P(P), .BASE(P.UNCORE_RAM_BASE), .RANGE(P.UNCORE_RAM_RANGE), .PRELOAD(P.UNCORE_RAM_PRELOAD)) ram (
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ram_ahb #(.P(P), .RANGE(P.UNCORE_RAM_RANGE), .PRELOAD(P.UNCORE_RAM_PRELOAD)) ram (
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.HCLK, .HRESETn, .HSELRam, .HADDR, .HWRITE, .HREADY,
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.HTRANS, .HWDATA, .HWSTRB, .HREADRam, .HRESPRam, .HREADYRam);
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end else assign {HREADRam, HRESPRam, HREADYRam} = '0;
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if (P.BOOTROM_SUPPORTED) begin : bootrom
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rom_ahb #(.P(P), .BASE(P.BOOTROM_BASE), .RANGE(P.BOOTROM_RANGE), .PRELOAD(P.BOOTROM_PRELOAD))
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rom_ahb #(.P(P), .RANGE(P.BOOTROM_RANGE), .PRELOAD(P.BOOTROM_PRELOAD))
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bootrom(.HCLK, .HRESETn, .HSELRom(HSELBootRom), .HADDR, .HREADY, .HTRANS,
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.HREADRom(HREADBootRom), .HRESPRom(HRESPBootRom), .HREADYRom(HREADYBootRom));
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end else assign {HREADBootRom, HRESPBootRom, HREADYBootRom} = '0;
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@ -271,7 +271,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
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end
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// global stall and flush control
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hazard #(P) hzu(
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hazard hzu(
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.BPWrongE, .CSRWriteFenceM, .RetM, .TrapM,
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.StructuralStallD,
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.LSUStallM, .IFUStallF,
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