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https://github.com/openhwgroup/cvw
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Fix SPI Delay1 behavior
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7964358651
commit
987015a2a7
@ -162,7 +162,7 @@ module spi_controller (
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// Counter for all four delay types
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if (DelayState & SCK & SCLKenable) begin
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DelayCounter <= DelayCounter + 8'd1;
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end else if (SCLKenable & EndOfDelay) begin
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end else if ((SCLKenable & EndOfDelay) | Transmitting) begin
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DelayCounter <= 8'd0;
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end
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@ -255,13 +255,13 @@ module spi_controller (
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else NextState = TRANSMIT;
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end
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HOLDMODE: begin
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if (EndTransmission) NextState = HOLD;
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else if (ContinueTransmit & HasINTERXFR) NextState = INTERXFR;
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if (EndOfFrame & HasINTERXFR) NextState = INTERXFR;
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else if (EndTransmission) NextState = HOLD;
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else NextState = TRANSMIT;
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end
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OFFMODE: begin
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if (EndTransmission) NextState = INACTIVE;
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else if (ContinueTransmit & HasINTERXFR) NextState = INTERXFR;
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if (EndOfFrame & HasINTERXFR) NextState = INTERXFR;
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else if (EndTransmission) NextState = HOLD;
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else NextState = TRANSMIT;
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end
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default: NextState = TRANSMIT;
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@ -269,14 +269,7 @@ module spi_controller (
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end
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SCKCS: begin // SCKCS case --------------------------------------
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if (EndOfSCKCS) begin
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if (~TransmitRegLoaded) begin
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// if (CSMode == AUTOMODE) NextState = INACTIVE;
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if (CSMode == HOLDMODE) NextState = HOLD;
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else NextState = INACTIVE;
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end else begin
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if (HasINTERCS) NextState = INTERCS;
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else NextState = TRANSMIT;
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end
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NextState = INTERCS;
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end else begin
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NextState = SCKCS;
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end
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@ -290,15 +283,18 @@ module spi_controller (
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end
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INTERCS: begin // INTERCS case ----------------------------------
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if (EndOfINTERCS) begin
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if (HasCSSCK) NextState = CSSCK;
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else NextState = TRANSMIT;
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if (TransmitRegLoaded) begin
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if (HasCSSCK) NextState = CSSCK;
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else NextState = TRANSMIT;
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end else NextState = INACTIVE;
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end else begin
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NextState = INTERCS;
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end
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end
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INTERXFR: begin // INTERXFR case --------------------------------
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if (EndOfINTERXFR) begin
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NextState = TRANSMIT;
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if (TransmitRegLoaded) NextState = TRANSMIT;
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else NextState = HOLD;
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end else begin
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NextState = INTERXFR;
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end
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