David Harris
f5e9c91193
All tests passing with bus interface
2021-02-24 07:25:03 -05:00
kaveh pezeshki
b36a5614b4
added comments for RAM and bootram, removed trailing whitepace
2021-02-23 21:28:33 -08:00
Noah Boorstin
c8e9edcc43
busybear: add bootram section in the same manner as ram
2021-02-24 02:02:28 +00:00
Noah Boorstin
a24270c4ca
busybear: add support for subwords in ram
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this is really weird and i'm not sure if i did it right. I'd love if @kaveh could review it
2021-02-24 01:51:18 +00:00
Noah Boorstin
00605864fc
busybear: start adding ram
2021-02-23 22:01:23 +00:00
Katherine Parry
8f5cc19143
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-02-23 20:21:53 +00:00
Katherine Parry
7b103423e1
inital FMA push
2021-02-23 20:19:12 +00:00
Noah Boorstin
d5e7a8a4cf
busybear: remove unused signals
2021-02-23 19:38:19 +00:00
Noah Boorstin
ceb7df3561
busybear: instantiate soc instead of hart
2021-02-23 18:59:06 +00:00
David Harris
c52a99ce2d
Fixed fetch stall after jump in bus unit
2021-02-23 09:08:57 -05:00
David Harris
817f81c356
Debugging Bus interface
2021-02-22 13:48:30 -05:00
kaveh pezeshki
62d9185212
Merge remote-tracking branch 'origin/tlb_toy' into busybear
2021-02-22 02:23:01 -08:00
Ross Thompson
9b3637bd87
RAS needs to be reset or preloaded. For now I just reset it.
...
Fixed bug with the instruction class.
Most tests now pass. Only Wally-JAL and the compressed instruction tests fail. Currently the bpred does not support compressed. This will be in the next version.
2021-02-19 20:09:07 -06:00
Ross Thompson
00de91cc87
Added FlushF to hazard unit.
...
Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
2021-02-19 16:36:51 -06:00
Ross Thompson
f25de68b7d
minor change to wave file.
2021-02-19 09:08:13 -06:00
Ross Thompson
c6ebe7733b
Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary.
...
About 149307ns of simulation run.
2021-02-18 21:32:15 -06:00
Thomas Fleming
21552eaf9d
Create simple TLB
...
This TLB is just a demonstration and is not currently
instantiated by the IFU or DFU.
2021-02-18 18:06:09 -05:00
David Harris
acd7ba8b60
Updated creation date of mul
2021-02-18 08:13:08 -05:00
Ross Thompson
de9e383bc6
Wrote a bash script to generate custom modelsim radix which maps instruction addresses into human readable lables.
...
Once combined with some simulation verilog this will display the current function in modelsim.
2021-02-17 22:20:28 -06:00
Ross Thompson
5df7e959f3
Integrated the branch predictor into the hardward. Not yet working.
2021-02-17 22:19:17 -06:00
David Harris
2f5b4c3a25
Resotred part of multiplier for lab 2
2021-02-17 16:14:04 -05:00
David Harris
64536dbc34
Removed multiplier for lab 2
2021-02-17 16:06:16 -05:00
David Harris
dc758a0c7b
Multiplier tweaks
2021-02-17 16:00:27 -05:00
David Harris
3edf910c18
Started to integrate OSU divider
2021-02-17 15:38:44 -05:00
David Harris
cb0054b524
Multiply instructions working
2021-02-17 15:29:20 -05:00
Noah Boorstin
5835641c6c
busybear testbench: check (almost) all the CSRs
2021-02-16 20:03:24 -05:00
Noah Boorstin
006f8c6c71
busybear: more small updates
...
not sure what to do about MMU yet, hopefully we'll decide at saturday's meeting
2021-02-16 20:01:00 -05:00
David Harris
8dec69c2ce
Added MUL
2021-02-15 22:27:35 -05:00
Ross Thompson
78db3654c6
We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS.
...
This is not yet tested but the system verilog does compile.
2021-02-15 14:51:39 -06:00
Teo Ene
a842879741
Added scripts to report power and area on a module-by-module basis
2021-02-15 12:09:33 -06:00
David Harris
f00728448a
WALLY ALU tests
2021-02-15 10:16:31 -05:00
David Harris
f6ec4a4548
Makefrag for ALU testsgen
2021-02-15 10:12:24 -05:00
David Harris
37dba8fd26
More memory interface, ALU testgen
2021-02-15 10:10:50 -05:00
Domenico Ottolia
75d9091fe8
Add privileged test cases
2021-02-14 17:01:46 -05:00
Ross Thompson
3ec1f668fc
added branch predictor 2 bit table + SRAM model. The SRAM model is only approximate, but it does correctly model the read and write pipelined behavior.
2021-02-14 15:13:55 -06:00
Teo Ene
dba5ce9c8b
Due to legacy code, make pnr would print out an internal Makefile error at the end of the run. While this error was inconsequential and did not affect anything, it still needed to be removed.
2021-02-14 13:43:30 -06:00
Ross Thompson
30df1cdd25
The top level of the branch predictor built and compiles. Does not yet function. Missing the BTB, RAS, and direction prediction tables.
2021-02-14 11:06:31 -06:00
Teo Ene
72dd97d9b6
sky130 18T and 15T cell libraries removed
...
Upon noticing their size, concerns were raised about available drive space.
As 12T is the main implementation focus, the decision was made to remove 15T and 18T.
Apologies if any were interested in implementing the processor across multiple standard cell libraries for comparison.
2021-02-14 09:05:41 -06:00
Teo Ene
e878a8bed2
After conferring with Dr. Harris, removed riscv-o3 submodule that most contributors to this repository lack access to.
2021-02-14 08:58:33 -06:00
Teo Ene
f3c902450b
After going through Lab 3 again, I've decided to make small changes to the provided floorplan so that it may serve as a slighly better example of a good floorplan.
2021-02-14 04:43:07 -06:00
Teo Ene
da6e9730a0
Cleaning up my code a little bit more
2021-02-14 02:58:25 -06:00
Teo Ene
83f7cd51e5
Final changes to the lab3 branch
...
- Removed manual register file placement script, as it has been removed from lab.
- Created pre-sets that only have to be uncommented for the changing clock target portion of lab.
- Cleaned up Makefile in case anyone looks inside of it.
2021-02-14 02:01:20 -06:00
Teo Ene
86fa5210f3
Commiting sample floorplan that I failed to commit last night
2021-02-13 12:08:03 -06:00
Teo Ene
ca7ee1d670
- Cleaned up unnecessary files
...
- Pulled updates for std cells
- Fixed typo that prevented easy switching between standard cell variants
- Fixed asynchronous reset paths from not being flagged as false
2021-02-12 21:49:42 -06:00
Shreya Sanghai
30bfd7534c
added branch tests
2021-02-12 22:40:08 -05:00
Teo Ene
9c4a117ffb
When Alex taught me how to use git, he stressed the importance of good commit messages that properly describe what changes were made
2021-02-12 16:52:23 -06:00
Teo Ene
db17d59698
Fixed rm bug for Ryan
2021-02-12 16:36:04 -06:00
Teo Ene
cc077da2bb
Removed riscv-o3 module
2021-02-12 16:08:34 -06:00
Teo Ene
f25b372c32
Quick commit for Ryan / branch / debugging.
2021-02-12 16:06:02 -06:00
Noah Boorstin
7312da1a99
busybear: allow testbench to ignore lack of MMU for now
...
I'd really like to go over this with someone else, not sure if this is
a good thing to be doing
If it is, we're at 1M instructions!
2021-02-12 20:08:56 +00:00
