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Configurable RISC-V Processor
154 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
Stata 2.3%
Other 4.2%
de9e383bc6
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Ross Thompson de9e383bc6 Wrote a bash script to generate custom modelsim radix which maps instruction addresses into human readable lables. 
Once combined with some simulation verilog this will display the current function in modelsim.
2021-02-17 22:20:28 -06:00
sky130 Added synth and PnR flow 2021-01-25 14:28:14 -06:00
wally-pipelined Wrote a bash script to generate custom modelsim radix which maps instruction addresses into human readable lables. 2021-02-17 22:20:28 -06:00
.gitignore Add the regression logs and new regression byproducts to the gitignore 2021-02-02 10:43:41 -05:00
.gitmodules After conferring with Dr. Harris, removed riscv-o3 submodule that most contributors to this repository lack access to. 2021-02-14 08:58:33 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor