Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity
Configurable RISC-V Processor
156 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
Stata 2.3%
Other 4.2%
72dd97d9b6
Go to file
Teo Ene 72dd97d9b6 sky130 18T and 15T cell libraries removed 
Upon noticing their size, concerns were raised about available drive space.
As 12T is the main implementation focus, the decision was made to remove 15T and 18T.

Apologies if any were interested in implementing the processor across multiple standard cell libraries for comparison.
2021-02-14 09:05:41 -06:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
wally-pipelined bus rw bugfix and peripherals testing 2021-02-12 00:02:45 -05:00
.gitignore Add the regression logs and new regression byproducts to the gitignore 2021-02-02 10:43:41 -05:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor