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Configurable RISC-V Processor
153 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
Stata 2.3%
Other 4.2%
83f7cd51e5
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Teo Ene 83f7cd51e5 Final changes to the lab3 branch 
- Removed manual register file placement script, as it has been removed from lab.
 - Created pre-sets that only have to be uncommented for the changing clock target portion of lab.
 - Cleaned up Makefile in case anyone looks inside of it.
2021-02-14 02:01:20 -06:00
sky130 - Cleaned up unnecessary files 2021-02-12 21:49:42 -06:00
wally-pipelined bus rw bugfix and peripherals testing 2021-02-12 00:02:45 -05:00
.gitignore Add the regression logs and new regression byproducts to the gitignore 2021-02-02 10:43:41 -05:00
.gitmodules Removed riscv-o3 module 2021-02-12 16:08:34 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor