Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity
Configurable RISC-V Processor
152 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
Stata 2.3%
Other 4.2%
8dec69c2ce
Go to file
David Harris 8dec69c2ce Added MUL
2021-02-15 22:27:35 -05:00
sky130 Added synth and PnR flow 2021-01-25 14:28:14 -06:00
wally-pipelined Added MUL 2021-02-15 22:27:35 -05:00
.gitignore Add the regression logs and new regression byproducts to the gitignore 2021-02-02 10:43:41 -05:00
.gitmodules After conferring with Dr. Harris, removed riscv-o3 submodule that most contributors to this repository lack access to. 2021-02-14 08:58:33 -06:00
LICENSE
README.md

README.md

riscv-wally

Configurable RISC-V Processor