Ross Thompson
c725b5534a
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-12-29 17:07:53 -06:00
Ross Thompson
654b10894c
Re-enabled the branch predictor in rv64gc.
2022-12-29 17:07:50 -06:00
Cedar Turek
4ed2c6255c
idiv passing radix 2, four copies
2022-12-27 22:10:48 -08:00
Cedar Turek
f48b7d7ef9
fpu idiv working on all configs with 1 copy of radix 2!
2022-12-26 23:18:28 -08:00
David Harris
2de66e9eef
Moved fdivsqrtexpcalc to its own file
2022-12-26 08:45:43 -08:00
cturek
ccbad67497
Added negative-result int diviison support in U and UM registers. 13 tests pass!
2022-12-22 16:25:37 +00:00
David Harris
e4579f3e9b
Removed CSR support from rv32i
2022-12-19 16:15:12 -08:00
Alessandro Maiuolo
2989782fe6
fixed LOGRK. FIxed Xs in WC and WS from muxes reliant on SqrtE. note not linting on 4 copies radix 4 because IntBits only 7 bits wide (need 8)
2022-12-18 19:04:36 -08:00
David Harris
2457448e29
Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE
2022-12-15 08:23:34 -08:00
David Harris
33aca5d35e
Added IDIV_ON_FPU flag to control whether integer division uses FPU
2022-12-15 06:37:55 -08:00
Ross Thompson
f9ffcf377b
Reverted the IROM/DTIM address range modelsim assignment.
2022-11-30 17:13:33 -06:00
cturek
9c70ab917c
Added A<B signal to fdivsqrt, started postprocessing merge
2022-11-13 22:40:26 +00:00
cturek
1e927df1a0
Added conditional OTFC swap for simplified int postprocessing
2022-11-06 23:09:09 +00:00
cturek
7567f388c2
Changed lzc names, started int/fp size merge in preproc
2022-11-06 22:21:35 +00:00
cturek
b893d9249d
Added new macros for int div preprocessing, added p, n, and rightshiftx logic
2022-11-06 21:53:48 +00:00
cturek
2ae0a9bb5d
Config Cleanup
2022-10-27 22:38:56 +00:00
cturek
a8a89f8dfc
unbroke DIVb
2022-10-26 16:11:51 +00:00
cturek
8475de128b
Config cleanup
2022-10-25 21:04:09 +00:00
Ross Thompson
403daecc8e
Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults.
...
The defaults are used for synthesis.
rv64i and rv32i: DTIM 2KiB, IROM 2KiB
rv32ic: DTIM 4KiB, IROM 16KiB
Regression tests require 8MiB or larger so modelsim overrides.
2022-10-11 10:47:13 -05:00
David Harris
e4c5754b3a
Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width
2022-10-10 09:10:55 -07:00
Ross Thompson
b52f593ecb
Reorganized the configs.
2022-10-09 16:46:48 -05:00
David Harris
f318daa605
Changed RV32i config to use DTIM and bus. Don't use this commit - it will break rv32i tests.
2022-10-05 11:46:52 -07:00
David Harris
437fd52bf6
Gated sticky bit in fdiv with SpecialCase
2022-09-20 20:05:00 -07:00
David Harris
cf5c513221
Restored radix 2 to pass regression
2022-09-20 19:30:16 -07:00
cturek
49a1259cf9
Fixed fgen4
2022-09-20 20:00:01 +00:00
David Harris
33af1f97f7
Define LOGNORMSHIFTSZ
2022-09-20 08:31:57 -07:00
David Harris
a36747fda0
Finished unified divsqrt otfc and fgen name changes
2022-09-19 08:30:59 -07:00
David Harris
1187187a5c
Divide testfloat starts with half-precision tests
2022-09-18 06:46:47 -07:00
David Harris
8438546d52
Fixed regression for divsqrt radix2
2022-09-07 06:12:23 -07:00
David Harris
e64f41f199
Checking in radix 4 square root with qsel, fgen, softc, but not working
2022-08-31 10:54:50 -07:00
David Harris
5956fbdd62
Fixed checking termination in testfloat testbench
2022-08-30 10:55:21 -07:00
David Harris
e526fea68a
fixed wally-config
2022-08-26 22:13:10 -07:00
David Harris
bd6f2444cd
Fixed address decoder hanging buildroot
2022-08-26 22:01:25 -07:00
David Harris
bf2c20cd17
Fixed DTIM/IROM_BASE number of bits in buildroot/fpga configs
2022-08-26 21:29:26 -07:00
David Harris
76006825b3
Set bit width of DMEM/IROM_SUPPORTED and fixed address decoding
2022-08-26 21:18:18 -07:00
David Harris
921a49921b
Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM
2022-08-26 21:05:20 -07:00
David Harris
460a95f99b
Added IROM and DTIM decoding to adrdecs
2022-08-26 20:45:43 -07:00
David Harris
6409548c8b
Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each
2022-08-26 20:26:12 -07:00
David Harris
906f6f2990
Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem
2022-08-26 20:12:03 -07:00
Ross Thompson
4ad7ccc7f7
Possible fixes for earily messup of rv32ic and rv64ic configs.
2022-08-25 14:42:08 -05:00
Ross Thompson
bd9401179d
BROKEN. Don't use this commit.
...
Issue running cacheless with bus.
2022-08-25 11:02:46 -05:00
Ross Thompson
b650d7e05a
Renamed RAM to UNCORE_RAM.
2022-08-24 18:09:07 -05:00
Ross Thompson
c6927d2ace
Modified the lsu/ifu memory configurations.
2022-08-24 12:35:15 -05:00
David Harris
7c91ed38a3
LSU minor edits
2022-08-23 07:35:47 -07:00
Katherine Parry
1accb92745
sqrt passes - lint warnings remain
2022-08-22 17:16:12 +00:00
Katherine Parry
8eeca3319c
radix-2 1 copy passes testfloat
2022-08-06 22:54:05 +00:00
Katherine Parry
8f1d8669b0
fixed fsw problem and removed 2 bit shift from shift correction
2022-08-03 22:16:51 +00:00
Ross Thompson
856ac24686
Removed replay from the config files.
2022-07-24 00:34:11 -05:00
Katherine Parry
ee7932c804
divider sizes reworked to match book
2022-07-22 22:02:04 +00:00
Katherine Parry
270216dd02
radix-4 division integrated into srt - not tested
2022-07-21 19:38:06 +00:00
