cvw/pipelined/config
2022-08-26 21:05:20 -07:00
..
buildroot Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each 2022-08-26 20:26:12 -07:00
fpga Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each 2022-08-26 20:26:12 -07:00
rv32e Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each 2022-08-26 20:26:12 -07:00
rv32gc Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each 2022-08-26 20:26:12 -07:00
rv32i Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each 2022-08-26 20:26:12 -07:00
rv32ic Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each 2022-08-26 20:26:12 -07:00
rv64BP Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM 2022-08-26 21:05:20 -07:00
rv64fp Added IROM and DTIM decoding to adrdecs 2022-08-26 20:45:43 -07:00
rv64fpquad Added IROM and DTIM decoding to adrdecs 2022-08-26 20:45:43 -07:00
rv64gc Added IROM and DTIM decoding to adrdecs 2022-08-26 20:45:43 -07:00
rv64i Added IROM and DTIM decoding to adrdecs 2022-08-26 20:45:43 -07:00
rv64ic Added IROM and DTIM decoding to adrdecs 2022-08-26 20:45:43 -07:00
shared Modified the lsu/ifu memory configurations. 2022-08-24 12:35:15 -05:00