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126 Commits

Author SHA1 Message Date
Katherine Parry
e251022269 merged floating-point radix-2 divider with radix-4 2022-07-15 20:16:59 +00:00
cturek
38bbd19abf Six tests passing and a bunch of sizizing issues fixed 2022-07-14 19:38:27 +00:00
Katherine Parry
b069cfbec2 fixed error in divsqrt 2022-07-14 18:16:00 +00:00
cturek
7629173b15 DIVLEN and counter updated for sqrt computation and rounding 2022-07-13 22:42:39 +00:00
cturek
d57fb6f98a radix 4 files removed from srt and divlen modified for sqrt 2022-07-13 19:46:48 +00:00
Katherine Parry
e05b2a07d2 removed warnings and took a mux out of the critical path 2022-07-12 18:32:17 -07:00
Katherine Parry
b728e5054d variable interations implemented in radix-4 divider 2022-07-11 18:30:21 -07:00
Katherine Parry
41c16be012 srt divider merged into fpu 2022-07-07 16:01:33 -07:00
Katherine Parry
08769e35ae modified wally shared 2022-07-07 21:59:43 +00:00
David Harris
88e3233935 Preliminary SRAM integration 2022-07-07 19:56:20 +00:00
Katherine Parry
1b4584e825 Renaming signals to match chapter 2022-07-03 12:26:22 -07:00
cturek
3a40c68549 Updated radix 2 divider to work with integers and floats in new structure. Integers still might not work. 2022-06-27 23:55:21 +00:00
Katherine Parry
06f7f9b147 fixed commented out error and removed killprod from result selection 2022-06-25 01:42:23 +00:00
slmnemo
7c019ea074 Removed references to initialization files 2022-06-23 16:50:27 -07:00
Katherine Parry
b54d84195f added radix-4 0/d handling 2022-06-23 22:36:19 +00:00
Katherine Parry
4a6dee5926 Testfloat running division - not passing 2022-06-23 00:07:34 +00:00
Katherine Parry
254ebf478e added fld in rv32 - needs testing 2022-06-20 22:53:13 +00:00
Katherine Parry
8425f8838d hopefully fixed lint error 2022-06-17 00:14:39 +00:00
Katherine Parry
31fd8772cf postprocessing unit created and passing all tests 2022-06-13 22:47:51 +00:00
DTowersM
dd34f25ffd changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability 2022-06-10 00:37:53 +00:00
Katherine Parry
8fa0fc4229 fma synth warnings and errors removed 2022-06-06 16:06:04 +00:00
Katherine Parry
8420b1e87c removed some debuging code accedentally pushed 2022-06-02 22:45:19 +00:00
Katherine Parry
cd8b2a2b98 added config rv64fpquad 2022-06-02 22:09:11 +00:00
Katherine Parry
03280c0f9c added createallvectors 2022-06-02 21:56:05 +00:00
Katherine Parry
9a09ee3a35 fpu paramaterized - except fdivsqrt 2022-06-02 19:50:28 +00:00
slmnemo
c16c5beef5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-02 02:52:03 +00:00
slmnemo
65961223f8 Updated Linux testbench to use new force/unforce method for Branch predictor init and removed related .txt files 2022-06-02 02:51:51 +00:00
Katherine Parry
e42afbfb30 paramerterized some small fma units 2022-06-01 23:34:29 +00:00
Katherine Parry
738bbf6479 Added fp tests - doesnpass yet 2022-05-19 16:32:30 +00:00
slmnemo
7656e3031c quit 2022-05-17 01:03:09 +00:00
David Harris
4f1b0fdc64 Preliminary support for big endian modes. Regression passes but no big endian tests written yet. 2022-05-08 06:46:35 +00:00
Kip Macsai-Goren
746fcfde30 set WFI timeout to after 16 bits of counting for all configs 2022-04-28 18:14:08 +00:00
Kip Macsai-Goren
2e0f45eab4 removed atomic, floating point from privileged tests configs 2022-04-25 19:13:15 +00:00
Kip Macsai-Goren
992cedbc52 Lowered WFI timeout wait time for privileged configs 2022-04-25 17:47:10 +00:00
bbracker
9eec1a83a6 deprecate unused LINUX_FIX_READ macro 2022-04-21 19:14:47 -07:00
Kip Macsai-Goren
8e72ace5ac fixed rv32ia to support clint and GPIO for priv tests 2022-04-20 17:31:34 +00:00
Shreya Sanghai
a8b3cc8cf9 added bpred size to wally config 2022-04-18 04:21:03 +00:00
David Harris
b4902a6ff9 First implementation of WFI timeout wait 2022-04-17 17:20:35 +00:00
Kip Macsai-Goren
fbcb0c0bd8 Added missing ZFH macro to new configs 2022-04-06 07:13:51 +00:00
Katherine Parry
c3d07b2c46 generating all testfloat vectors 2022-04-04 17:17:12 +00:00
Kip Macsai-Goren
37c755e6ce added RV64IA config to have a config without compressed instructions 2022-04-02 18:24:08 +00:00
Ross Thompson
51dfa16f59 Updated the fpga test bench. 2022-04-01 17:14:47 -05:00
Ross Thompson
33b9b5423d reverted temporary change to configs. 2022-03-22 22:31:34 -05:00
Ross Thompson
c233ef9768 Reverted change to configuration which caused issue with lint. 2022-03-22 21:44:08 -05:00
Katherine Parry
e3d01c875b FMA parameterized and FMA testbench reworked 2022-03-19 19:39:03 +00:00
Ross Thompson
67ff8f27f4 Can now support the following memory and bus configurations. 
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
 2022-03-11 15:18:56 -06:00
bbracker
a8e8cfb838 switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv 2022-03-01 03:11:43 +00:00
bbracker
202bd2f8f8 change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests 2022-02-22 03:46:08 +00:00
Ross Thompson
0bd533473c New config option to enable hptw writes to PTE in memory to update Access and Dirty bits. 2022-02-17 17:19:41 -06:00
Ross Thompson
4273775a2b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 14:22:19 -06:00
David Harris
510b47523a rv32e config update 2022-02-08 17:59:50 +00:00
Ross Thompson
853a7bba18 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-08 11:36:30 -06:00
Ross Thompson
8a2ee22395 Finished merge. 2022-02-08 11:36:24 -06:00
David Harris
64e9f4c0d3 Restored E tests to makefrag 2022-02-08 16:41:11 +00:00
David Harris
c61cd55c5c Merged TIM and regular testbenches. RV32e now working and back in regression. 2022-02-08 12:18:13 +00:00
Ross Thompson
d21be9d998 Added config to allow using the save/restore or replay implementation to handle sram clocked read delay. 2022-02-04 23:49:07 -06:00
David Harris
0f7b8017d1 Modified regression to use proper rv32e test name, but rv32e_wally32e still isn't passing due to loop exceeding iteration limit 2022-02-05 05:35:51 +00:00
David Harris
72bc64ef28 Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests. 2022-02-05 04:16:18 +00:00
David Harris
fb041fe06a rv32e 2022-02-04 01:56:30 +00:00
David Harris
ef5af9b5fd renamed configs 2022-02-03 23:36:41 +00:00
David Harris
38bbe23d14 More config file cleanup; 32ic tests broken 2022-02-03 01:08:34 +00:00
David Harris
da8819d64b changed DMEM and IMEM configurations to support BUS/TIM/CACHE 2022-02-03 00:41:09 +00:00
David Harris
68a6b4af3d Removed Busybear and Buildroot Configuration 2022-02-02 20:32:22 +00:00
David Harris
4ba37d5cc0 Config file & wally-riscv-arch-test cleanup 2022-02-02 16:35:52 +00:00
David Harris
090533cfe9 Replaced || and && with | and & 2022-01-31 01:07:35 +00:00
David Harris
448acedd8b Set up rv32emc config 2022-01-27 14:37:58 +00:00
David Harris
748375c82f Updated configs to fix GPIO address to match FU540 2022-01-26 18:16:34 +00:00
David Harris
b63e53bbdb Defined rv32e and rv32emc configs 2022-01-17 14:01:01 +00:00
Ross Thompson
3bec276862 Added tim only test to regression-wally. Minor cleanup to ifu. 2022-01-14 11:13:06 -06:00
Ross Thompson
a973681a90 Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon. 2022-01-13 22:21:43 -06:00
Ross Thompson
aad28366d7 Partial local dtim in lsu configuration. 2022-01-13 17:50:31 -06:00
Ross Thompson
960af4b70f Set rv32ic to not use icache. 2022-01-12 14:10:09 -06:00
David Harris
401a5b1779 Removed unused coremark_bare 2022-01-10 05:05:55 +00:00
David Harris
39d5570d2c Added riscvsingle. Removed unnecessary coremark config. Added compiler flags for Coremark. 2022-01-10 05:04:13 +00:00
Ross Thompson
06168e67e4 Switched block for line in caches. 2022-01-04 22:08:18 -06:00
David Harris
b36ace221e Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00