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e73e16e57a
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Author SHA1 Message Date
Ross Thompson
e73e16e57a Created special test for driving the instruction spill error. 
The extact problem occurs when a 4 byte instruction startles two cache blocks (or without a cache two ahbi words) and the code jumps to a cache block other than the next cache block. Consider the following sample of code.

0000000000000080 <test_spill>:
  80:	42a9                	li	t0,10
  82:	0001                	nop
  84:	0001                	nop
  86:	0001                	nop
  88:	02bd                	addi	t0,t0,15
  8a:	00628e33          	add	t3,t0,t1
  8e:	01ce8963          	beq	t4,t3,a0 <match>

0000000000000092 <failure>:
  92:	557d                	li	a0,-1
  94:	8082                	ret
  96:	00000013          	nop
  9a:	00000013          	nop
  9e:	0001                	nop

00000000000000a0 <match>:
  a0:	1ffd                	addi	t6,t6,-1
  a2:	fc0f9fe3          	bnez	t6,80 <test_spill>
  a6:	4501                	li	a0,0
  a8:	8082                	ret

Instructions 0x88, 0x8a and 0x8e are read incorrectly.  However once the branch predictor begins to correctly predict the beq at 0x8e the instrution at 0xa0 is loaded incorrectly as the 2 upper bytes of 0x8e and the two bytes of 0x92.  This amalgamation causes c.addi at 0xa0 to do something else and the loop never terminates.

The button of wavefile wave.do shows the exact problem in the 'icache'.
 2021-04-08 15:05:08 -05:00
Ross Thompson
4322694f7a Switch to use RV64IC for the benchmarks. 
Still not working correctly with the icache.

instr
addr   correct   got
 2021-04-07 19:12:43 -05:00
Ross Thompson
c91436d3b7 Merge branch 'icache_bp_bug' into tests 
Not sure this merge is right.
 2021-04-06 21:46:40 -05:00
Ross Thompson
98a04abe6c Merge remote-tracking branch 'refs/remotes/origin/tests' into tests 2021-04-06 21:20:55 -05:00
Ross Thompson
bff2d61a1f Steps to getting branch predictor benchmarks running. 2021-04-06 21:20:51 -05:00
Jarred Allen
bd8f1eea3c Fix another bug in icache 2021-04-06 17:47:00 -04:00
Jarred Allen
3afc358974 Fix another bug in icache 2021-04-06 12:48:42 -04:00
Jarred Allen
c95da7d11e Fix bug in icache 2021-04-03 18:10:54 -04:00
Shreya Sanghai
df149d1be7 fixed minor bugs in localHistory 2021-04-01 13:40:08 -04:00
ShreyaSanghai
28a9c6ba56 added localHistoryPredictor 2021-04-01 22:22:40 +05:30
Shreya Sanghai
b544526766 fixed bugs in global history to read latest GHRE 2021-03-31 21:56:14 -04:00
Ross Thompson
9172e52286 Corrected a number of bugs in the branch predictor. 
Added performance counters to individually track
branches; jumps, jump register, jal, and jalr; return.
jump and jump register are special cases of jal and jalr.
Similarlly return is a special case of jalr.
Also added counters to track if the branch direction was wrong,
btb target wrong, or the ras target was wrong.
Finally added one more counter to track if the BP incorrectly predicts
a non-cfi instruction.
 2021-03-31 11:54:02 -05:00
Ross Thompson
a64a37d702 Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally. 2021-03-30 23:18:20 -05:00
Ross Thompson
2a308309e4 fixed some bugs with the RAS. 2021-03-30 13:57:40 -05:00
Jarred Allen
6e83ccc3c4 Comment out failing tests 2021-03-30 13:07:26 -04:00
Jarred Allen
108f18e580 Merge branch 'cache' into main 2021-03-30 12:56:19 -04:00
Jarred Allen
7ca57cc4fc Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/regression/wave-dos/ahb-waves.do
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-busybear.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 12:55:01 -04:00
David Harris
eefeae58fa Added WALLY-PIPELINE to make 2021-03-26 13:13:13 -04:00
David Harris
8723fb916c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-26 13:04:52 -04:00
David Harris
637bba6509 Added fp test to testbench 2021-03-26 13:03:23 -04:00
Noah Boorstin
b5a1691c2b Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-busybear.sv
 2021-03-26 12:26:30 -04:00
Shreya Sanghai
339bd5d3eb Merge branch 'PPA' into main 
Conflicts:
	wally-pipelined/testbench/testbench-privileged.sv
 2021-03-25 20:35:21 -04:00
Shreya Sanghai
cc988f420f removed minor bugs 2021-03-25 20:29:50 -04:00
ShreyaSanghai
139c2076a1 Removed PCW and InstrW from ifu 2021-03-26 01:53:19 +05:30
Noah Boorstin
05d362e334 regression: use busybear batch instead 2021-03-25 15:34:10 -04:00
Domenico Ottolia
56a32b5882 More bug fixes for privileged tests 2021-03-25 15:05:55 -04:00
Noah Boorstin
44060b579b busybear: quick fix to mem reading 
also stop ignoring mcause at the start
 2021-03-25 14:29:11 -04:00
Brett Mathis
162f2df880 FPU Pipeline completed - can begin integration 2021-03-25 13:29:03 -05:00
Domenico Ottolia
f134b09a97 Fix bugs with privileged tests 2021-03-25 14:06:05 -04:00
Noah Boorstin
d02c88dab5 busybear: stop NOPing out atomics 
and bump regression to check for 800k instrs, up from 200k
 2021-03-25 13:29:56 -04:00
David Harris
ee36f4e09b Added WALLY-PIPELINE test to rv64wally 2021-03-25 13:18:50 -04:00
David Harris
eb9787609e testgen-PIPELINE python startup 2021-03-25 13:12:18 -04:00
Shriya Nadgauda
21989ee615 adding PIPELINE tests 2021-03-25 13:07:25 -04:00
Jarred Allen
b774d35c34 Output NOP instead of BAD when reset 2021-03-25 12:42:48 -04:00
Jarred Allen
4b92a595ab Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/uncore/dtim.sv
 2021-03-25 12:10:26 -04:00
Teo Ene
51291949d8 Config file for ppa experiments 2021-03-25 10:23:21 -05:00
David Harris
a8abd47fbc Added PPA README 2021-03-25 11:21:31 -04:00
Thomas Fleming
e3900bd0fa Finish finite state machines for page table walker 2021-03-25 02:48:40 -04:00
Thomas Fleming
7367052e76 Add vscode and pycache folders to .gitignore 2021-03-25 02:37:50 -04:00
Thomas Fleming
b5003b093a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-25 02:35:21 -04:00
bbracker
a3788eb218 added 1 tick delay to dtim flops 2021-03-25 02:23:30 -04:00
bbracker
b5fa410e15 added 1 tick delay on tim reads 2021-03-25 02:15:28 -04:00
Jarred Allen
682050a33b Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/ifu/ifu.sv
 2021-03-25 00:51:12 -04:00
bbracker
67b27cd2f5 instrfault direspecting stalls bugfix 2021-03-25 00:44:35 -04:00
bbracker
02e924e55a instrfaults not respecting stalls bugfix 2021-03-25 00:16:26 -04:00
bbracker
1e3f683a9d upgraded gpio bus interface 2021-03-25 00:15:02 -04:00
bbracker
717257d9ac gitignore FunctionRadix.addr 2021-03-25 00:13:46 -04:00
bbracker
e98dd420bc future work comment about suspicious-looking verilog in csri.sv 2021-03-25 00:10:44 -04:00
Thomas Fleming
b1d849c822 Add all PMP addr registers 2021-03-24 21:58:33 -04:00
Teo Ene
f5b70c8ab8 Manual assembly hack to prevent RV64IM coremark from EBREAKing early 2021-03-24 18:05:34 -05:00