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Configurable RISC-V Processor
473 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
Stata 2.3%
Other 4.2%
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Noah Boorstin 44060b579b busybear: quick fix to mem reading 
also stop ignoring mcause at the start
2021-03-25 14:29:11 -04:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
wally-pipelined busybear: quick fix to mem reading 2021-03-25 14:29:11 -04:00
.gitignore Add vscode and pycache folders to .gitignore 2021-03-25 02:37:50 -04:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor