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Author SHA1 Message Date
Teo Ene
a3aa103dc7 Fix typo from last commit 2021-03-24 17:09:58 -05:00
Teo Ene
4427b5ec01 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-24 17:04:48 -05:00
Teo Ene
e43849b82c Updated coremark_bare testbench for IM 2021-03-24 17:04:43 -05:00
Katherine Parry
18cb1f4873 fixed various bugs in the FMA 2021-03-24 21:51:17 +00:00
Teo Ene
385ce9a8f9 Added BPTYPE to coremark_bare config 2021-03-24 16:38:29 -05:00
Ross Thompson
a99c0502e5 Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions. 2021-03-24 15:56:55 -05:00
Ross Thompson
11109e5a88 Updated the function radix to have a new name FunctionName and it now pervents false transisions from the current function name when the PCD is flushed. 2021-03-24 13:03:43 -05:00
Domenico Ottolia
d67e28bf50 re-organize privileged tests to be in rv64p to rv32p folders 2021-03-24 13:51:25 -04:00
Jarred Allen
c1fe16b70b Give some cache mem inputs a better name 2021-03-24 12:31:50 -04:00
Ross Thompson
d74b6eb69c Updated the .gitignore to reject all the extra compiled objects for the branchmarks. 2021-03-24 10:30:19 -05:00
Ross Thompson
efa8ad4e17 Edited sieve to work with wally. It was using the time of day to compute runspeed; however this functionality does not yet work in the wally software stack. 2021-03-24 09:22:21 -05:00
Jarred Allen
a51257abca Fix compile errors from const not actually being constant (why does Verilog do this) 2021-03-24 00:58:56 -04:00
Ross Thompson
1c6e37120e Fixed RAS errors. Still some room for improvement with the BTB and RAS. 2021-03-23 23:00:44 -05:00
Jarred Allen
4410944049 Merge branch 'main' into cache 2021-03-23 23:35:36 -04:00
Ross Thompson
84ad1353e4 Fixed a bunch of bugs with the RAS. 2021-03-23 21:49:16 -05:00
Katherine Parry
56dc8de009 fixed various bugs in the FMA 2021-03-24 01:35:32 +00:00
Ross Thompson
4fb7a1e0a6 Fixed the valid bit issue. Now the branch predictor is actually predicting instructions. 2021-03-23 20:20:23 -05:00
Ross Thompson
49348d734b fixed issue with BTB's valid bit not updating. There is still a problem is valid not ocurring in the correct clock cycle. 2021-03-23 20:06:45 -05:00
Ross Thompson
95dbc5f1fa fixed a whole bunch of bugs with the branch predictor. Still an issue with how PCNextF is not updated because the CPU is stalled. 2021-03-23 16:53:48 -05:00
Jarred Allen
d6ecc3ede0 Begin work on direct-mapped cache 2021-03-23 17:03:02 -04:00
Teo Ene
ef3d2dda48 Added BOOTTIM to InstrAccessFaultF calculation in uncore/imem 2021-03-23 15:21:13 -05:00
Ross Thompson
174557ae89 Simulation definitely shows the branch predictor counters and branch predictor don't work. :( 2021-03-23 14:04:58 -05:00
Ross Thompson
5edc90b1c2 added a whole bunch of interseting test code for branches which does not work. 2021-03-23 13:54:59 -05:00
Ross Thompson
6a050219d4 updated the branch predictor config. 2021-03-23 13:54:59 -05:00
Ross Thompson
9e61481414 Added first benchmark. 2021-03-23 13:54:59 -05:00
Ross Thompson
2b0f7cdd42 Temporary exe2memfile0.pl script to support starting addresses of 0. 2021-03-23 13:54:59 -05:00
Ross Thompson
e1842c8da6 Broken commit. Trying to get exe2memfile.pl to work correctly with non 0x8000_0000 starting addresses. 2021-03-23 13:54:59 -05:00
Noah Boorstin
69e5319675 busybear: more progress 2021-03-23 14:49:30 -04:00
Shreya Sanghai
1d6a2989ed PC counts branch instructions 2021-03-23 14:25:51 -04:00
Jarred Allen
0d05c51af9 Remove deleted signal from waves 2021-03-23 14:17:17 -04:00
Noah Boorstin
24e403bc35 busybear: more progress moving from instrf to instrrawd 2021-03-23 14:06:21 -04:00
Noah Boorstin
f3194c6388 busybear: ignore illegal instruction when starting 2021-03-23 13:28:56 -04:00
Jarred Allen
7da8af4c68 Another tweak to regression-wally.py comments 2021-03-23 00:18:38 -04:00
Jarred Allen
0f8fe8fb3b Document some internal signals 2021-03-23 00:10:35 -04:00
Jarred Allen
6ffa01cc4d Add comments explaining icache inputs 2021-03-23 00:07:39 -04:00
Jarred Allen
82de84469f Slight change to regression-wally.py comments 2021-03-23 00:02:40 -04:00
Jarred Allen
827993598d Small commit to see if new hook tests non-main branch 2021-03-22 23:57:01 -04:00
Noah Boorstin
d5bd5fa9d7 start migrating busybear over to InstrRawD/PCD 
this breaks busybear for now
 2021-03-22 23:45:04 -04:00
Noah Boorstin
15474f678d Merge branch 'main' into cache 2021-03-22 23:28:30 -04:00
Noah Boorstin
849641f31e busybear: add better warning on illegal instruction 
...also it seems that mret is being picked up as an illegal instruction??
 2021-03-22 18:24:35 -04:00
Noah Boorstin
34b8f750ce busybear: temporarially force rf[5] correct after failure to read CSR 2021-03-22 18:12:41 -04:00
Noah Boorstin
77dd0b4504 busybear: allow overwriting read values 2021-03-22 17:28:44 -04:00
Noah Boorstin
7bb31c3287 busybear: finally get the right error 2021-03-22 16:52:22 -04:00
bbracker
5efd5958e7 added delays to uart AHB signals 2021-03-22 15:40:29 -04:00
Jarred Allen
6ce52f9b80 Remove DelaySideD since it isn't needed 2021-03-22 15:13:23 -04:00
Jarred Allen
b871bfe714 Update icache interface 2021-03-22 15:04:46 -04:00
Noah Boorstin
2aa76b27e1 busybear: comment out some debug printing 2021-03-22 14:54:05 -04:00
Jarred Allen
3f897bbf53 Merge branch 'main' into cache 2021-03-22 14:50:22 -04:00
Noah Boorstin
74bcd9b994 regression: expect 200k instead of 100k busybear instrs 
and a minor busybear bugfix
 2021-03-22 14:47:52 -04:00
Jarred Allen
3748d03adc Merge branch 'main' into cache 2021-03-22 13:47:48 -04:00