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Configurable RISC-V Processor
423 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
SystemVerilog 8.2%
Python 2.7%
Stata 2.3%
Other 4.2%
28a9c6ba56
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ShreyaSanghai 28a9c6ba56 added localHistoryPredictor
2021-04-01 22:22:40 +05:30
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
testsBP Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions. 2021-03-24 15:56:55 -05:00
wally-pipelined added localHistoryPredictor 2021-04-01 22:22:40 +05:30
.gitignore Updated the .gitignore to reject all the extra compiled objects for the branchmarks. 2021-03-24 10:30:19 -05:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor