Noah Boorstin
4a8b689f62
busybear: better NOPing out of float instructions
2021-03-08 21:24:19 +00:00
Noah Boorstin
c780a25f92
busybear: better instrF checking
...
So this now checks instrF only when StallD is low. @kaveh I'd love your
opinion on this. I don't know if this is a good idea or not. Ideally we
should probably be checking InstrRawD instead, but I kind of want to stay
checking the instr in the F stage instead of D for now. Idk if this is worth
staying in F, I can't really see any big downsides to checking the instruction in
D except that PCD isn't an external signal, but neither is StallD, so.....
Anyway I'd love others' thoughts on this
2021-03-08 19:48:12 +00:00
Noah Boorstin
1b206d5a3c
busybear: make a second .do file with better optimization for command line mode
2021-03-08 19:35:00 +00:00
Noah Boorstin
93c9c57426
busybear: load mem files from verilog instead of .do
2021-03-08 19:26:26 +00:00
David Harris
9c7da510fb
Created atomic test vector and directories
2021-03-08 09:38:55 -05:00
Ross Thompson
d5f151eb0f
Updated the paths to the branch predictor memory preloads for busy bear.
2021-03-05 15:36:00 -06:00
Ross Thompson
87ed6d510c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-05 15:27:22 -06:00
Ross Thompson
301166d062
Oups. I forgot to update other do files with the commands to preload the branch predictor memories.
2021-03-05 15:23:53 -06:00
Thomas Fleming
2b891196d9
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-05 16:20:53 -05:00
Noah Boorstin
3c5be59e9b
busybear: add branch preditor loading to do file
...
(sorry to add more loading to the do instead of less)
2021-03-05 21:01:41 +00:00
Thomas Fleming
be6ee84d87
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-05 15:46:51 -05:00
Noah Boorstin
86142e764a
Merge branch 'main' into busybear
2021-03-05 20:27:19 +00:00
Noah Boorstin
889d2c0b85
fix wally-pipelined-batch.do to match wally-pipelined.do
2021-03-05 20:27:01 +00:00
bbracker
850a2e9329
added a delay to sel signals
2021-03-05 15:07:34 -05:00
bbracker
77e2e357a7
more merging fixes
2021-03-05 14:36:07 -05:00
bbracker
ed4ff1ecd0
remove deprecated mem signals
2021-03-05 14:27:38 -05:00
bbracker
19fc7d2381
refactored sim file
2021-03-05 14:25:16 -05:00
bbracker
0f4a231543
first merge of ahb fix
2021-03-05 14:24:22 -05:00
Noah Boorstin
1a11b60664
busybear: slight testbench update
2021-03-05 19:00:40 +00:00
Thomas Fleming
2e2eb5839f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-05 13:35:44 -05:00
Thomas Fleming
8c97143be6
Place tlb parameters into constant header file
2021-03-05 13:35:24 -05:00
Thomas Fleming
7e11317a2d
Export SATP_REGW from csrs to MMU modules
2021-03-05 01:22:53 -05:00
Noah Boorstin
f48af209c4
busybear: make CSRs only weird for us
2021-03-05 00:46:32 +00:00
Noah Boorstin
5a3ba1174e
busybear: better implenetation of sim-busybear-batch
2021-03-05 00:39:03 +00:00
Ross Thompson
a662aa487c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-04 17:31:27 -06:00
Ross Thompson
264480f258
updated the function radix to look at wally signals.
2021-03-04 17:31:12 -06:00
Jarred Allen
41f682f848
Partial progress towards compressed instructions
2021-03-04 18:30:26 -05:00
Noah Boorstin
dfae278ffb
busybear: make imperas tests work again
2021-03-04 22:44:49 +00:00
Katherine Parry
cfac6bf0c7
fixed various bugs
2021-03-04 22:20:39 +00:00
Katherine Parry
09564f1c77
fixed various bugs
2021-03-04 22:20:28 +00:00
Katherine Parry
a6bc39b5ad
fixed various bugs
2021-03-04 22:20:23 +00:00
Katherine Parry
526e3f5996
fixed various bugs
2021-03-04 22:20:02 +00:00
Katherine Parry
1e906b36a0
fixed various bugs
2021-03-04 22:19:21 +00:00
Katherine Parry
3fb0f323b8
fixed various bugs
2021-03-04 22:18:47 +00:00
Katherine Parry
fdfc0dbf46
fixed various bugs
2021-03-04 22:18:19 +00:00
Ross Thompson
fafecb5f01
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-04 16:06:22 -06:00
Jarred Allen
106718b196
Remove rd2, working for non-compressed
2021-03-04 16:46:43 -05:00
Brett Mathis
57e484cd55
Pipelined functional units for FPU
2021-03-04 14:30:11 -06:00
Thomas Fleming
3303a013ef
Merge branch 'walker' into main
2021-03-04 15:27:03 -05:00
Noah Boorstin
735c6789ea
busybear: comment out instraccessfaultf for imem for now
2021-03-04 20:26:41 +00:00
Thomas Fleming
1fb50aff6b
Add reference output for mmu test
2021-03-04 15:17:49 -05:00
Noah Boorstin
827dfd774b
Merge branch 'main' into busybear
...
Conflicts:
wally-pipelined/src/uncore/imem.sv
2021-03-04 20:16:03 +00:00
Ross Thompson
66e84f3a2c
Merge branch 'bp' into main
...
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
2021-03-04 13:35:46 -06:00
Ross Thompson
4d14c714a7
Fixed forwarding around the 2 bit predictor.
2021-03-04 13:01:41 -06:00
Thomas Fleming
7347b3e1b7
Fix some constants in virtual memory test
2021-03-04 13:19:55 -05:00
Shreya Sanghai
246dbd05e7
fixed bugs
2021-03-04 12:59:45 -05:00
Shreya Sanghai
f0ec365117
added performance counters
2021-03-04 11:42:52 -05:00
bbracker
448cba2a5b
JALR testing
2021-03-04 10:37:30 -05:00
bbracker
d98c69c4c6
changed test maker to output trace files for debug
2021-03-04 10:36:04 -05:00
Ross Thompson
52d95d415f
Converted to using the BTB to predict the instruction class.
2021-03-04 09:23:35 -06:00
