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Configurable RISC-V Processor
519 Commits 14 Branches 1 Tag 31 MiB
Assembly 55.4%
C 27.2%
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Python 2.7%
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Ross Thompson 4322694f7a Switch to use RV64IC for the benchmarks. 
Still not working correctly with the icache.

instr
addr   correct   got
2021-04-07 19:12:43 -05:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
testsBP Switch to use RV64IC for the benchmarks. 2021-04-07 19:12:43 -05:00
wally-pipelined Switch to use RV64IC for the benchmarks. 2021-04-07 19:12:43 -05:00
.gitignore Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally. 2021-03-30 23:18:20 -05:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor